Clock Signal Generation Circuit for Minimum Delay Duty Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor apparatuses face challenges in maintaining accurate phase and duty ratio synchronization of clock signals due to phase skew and duty ratio distortion, which existing duty correction circuits struggle to address effectively.
Innovation Solution
A signal generation circuit comprising a first and second delay circuit and a duty control circuit, where the duty control circuit compares the phases of output signals and adjusts delay times to minimize phase differences and duty ratios, ensuring optimal synchronization by decreasing delay times uniformly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a general duty correction circuit sets any one of a plurality of clock signals to a reference clock signal and adjusts phase differences, then phase skew and duty ratio distortion are compensated, but delay time increases and operational speed decreases
Solution Approach 1:
The patent changes the delay time parameter dynamically by detecting the phase of output signals and adjusting delay control signals to minimize delay time while maintaining phase skew compensation. This allows the circuit to operate at maximum speed without sacrificing synchronization accuracy.
Solution Approach 2:
The duty correction circuit automatically detects phase differences and adjusts its own delay parameters without external intervention. The circuit monitors its own output signals and self-regulates the delay time to achieve optimal performance, eliminating the need for manual tuning or external control.
2Reliability
If delay circuits are used to adjust phase differences between clock signals, then synchronization is improved, but circuit complexity increases
Solution Approach 1:
The delay control circuit serves multiple functions: it detects phase differences, generates appropriate delay control signals, and adjusts delay times for multiple clock signals simultaneously. This multi-functionality reduces the need for separate circuits for each function, thereby simplifying the overall circuit architecture while maintaining synchronization accuracy.
Solution Approach 2:
The patent combines the phase detection function and delay adjustment function into a single integrated duty correction circuit. By merging these functions, the circuit avoids the complexity of having separate detection and adjustment circuits, reducing the total number of components while achieving the same synchronization performance.
3Reliability
If delay control signals are increased to compensate for phase skew, then phase synchronization is improved, but delay time increases reducing productivity
Solution Approach 1:
The patent implements dynamic adjustment of delay time based on real-time phase detection. Instead of using a fixed or maximized delay value, the circuit continuously monitors output signal phases and adjusts delay control signals to achieve the minimum necessary delay for synchronization. This dynamic approach maintains phase synchronization while minimizing delay time to maximize signal generation speed.
Data Source
AI summary
A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.