Clock Signal Generation Circuit for Phase Alignment With Minimum Delay

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Solution Overview

Problem

Semiconductor apparatuses face challenges in maintaining precise phase and duty ratio alignment of clock signals due to circuit characteristics, leading to phase skew and duty ratio distortion, which existing duty correction circuits struggle to effectively address.

Innovation Solution

A signal generation circuit comprising delay circuits and a duty control circuit that compares phases of output signals and adjusts delay times to minimize phase differences and duty ratios by decreasing delay times uniformly, ensuring optimal operation characteristics and speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a general duty correction circuit sets one clock signal as reference and adjusts phase differences of other clock signals, then phase skew and duty ratio distortion can be compensated, but the delay time of the correction circuit increases

Engineering Contradiction:
Improvephase alignment precisionVSAvoiddelay time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the delay time parameter of the delay circuit dynamically. Initially, a relatively large delay time is used to ensure accurate phase alignment and duty ratio correction. After correction is complete, the delay time is reduced to minimize the impact on signal processing speed. This parameter switching resolves the contradiction between achieving precise correction and maintaining fast signal processing.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If delay circuits are used to adjust phase differences between clock signals, then phase skew can be corrected, but the operation speed of the signal generation circuit decreases

Engineering Contradiction:
Improvephase alignment precisionVSAvoidoperation speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent makes the delay time dynamic rather than fixed. The delay circuit operates with a larger delay time during the phase alignment phase, then transitions to a smaller delay time during normal operation. This dynamic adjustment allows the system to achieve both accurate phase alignment and high operation speed, resolving the contradiction between precision and speed.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If the delay time is increased to ensure accurate duty ratio correction, then phase skew compensation improves, but the overall circuit delay increases

Engineering Contradiction:
Improveduty ratio precisionVSAvoidcircuit delay
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent performs duty ratio correction and phase alignment as preliminary actions before normal signal processing. During this initial phase, the delay circuit uses a larger delay time to ensure accurate correction. Once the correction is complete, the delay time is reduced for subsequent operations. This preliminary action approach ensures high precision correction without permanently increasing circuit delay.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11349457B2Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method
Publication Date: 2022.05.31 SK HYNIX INC
  • US11349457B2 patent drawing
  • US11349457B2 patent drawing
  • US11349457B2 patent drawing

AI summary

A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.