Clock Skew Control Circuit to Avoid Double Cycle Compression
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Solution Overview
Problem
Controlling skew between multiple clock signals in semiconductor circuits is challenging, particularly when data exchange occurs across different clock domains, as existing methods often result in either shortening delays for both clocks simultaneously or decreasing the delay of the later clock first, which can lead to data transmission issues and increased setup times.
Innovation Solution
A skew control circuit employing programmable delay elements, a skew detector arrangement, and a control circuit that determines the order of edge occurrences to selectively adjust delays, deferring adjustments to avoid double cycle compression and ensure proper data exchange across clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If delays for both clock signals are shortened simultaneously, then skew between clock signals is reduced, but setup time requirements are violated and data transmission reliability deteriorates
Solution Approach 1:
The patent segments the delay adjustment process by introducing a deferral mechanism that divides the simultaneous adjustment of multiple clock signals into sequential steps. When skew detection indicates that both clock signals require delay shortening, the system segments this operation by first adjusting one clock signal and deferring the adjustment of the other to a subsequent cycle, thereby preventing setup time violations while still reducing overall skew.
Solution Approach 2:
The patent applies preliminary action by detecting skew conditions in advance and using a deferral mechanism to prepare adjustment sequences that prevent harmful double compression before it occurs. The skew detector arrangement identifies when both clock signals require adjustment, and the control logic preemptively schedules sequential adjustments rather than allowing simultaneous changes that would violate setup times.
2Productivity
If delay adjustment is performed for multiple clock signals in the same cycle, then skew control efficiency is improved, but double cycle compression occurs causing timing restrictions to be violated
Solution Approach 1:
The patent implements periodic action by using a deferral mechanism that distributes delay adjustments across multiple clock cycles rather than concentrating them in a single cycle. When skew detection indicates that multiple clock signals require adjustment, the system schedules these adjustments periodically across successive cycles, preventing double cycle compression while maintaining effective skew control over time.
3Device complexity
If skew adjustment is performed without considering edge occurrence order, then control circuit complexity is reduced, but precision of skew control deteriorates due to double cycle compression
Solution Approach 1:
The patent applies preliminary action by detecting and recording the order of edge occurrences for multiple clock signals before performing skew adjustment. The skew detector arrangement identifies which clock signal edges occur first, second, and third, and this preliminary information is used by the control logic to schedule delay adjustments in the correct sequence, preventing double cycle compression while maintaining relatively simple circuit implementation.
Data Source
AI summary
The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.