Configurable Clock Skew Layout for Time-Borrowing Circuits
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Solution Overview
Problem
Conventional time borrowing schemes in integrated circuits face limitations in achieving optimal performance due to limited delays and complexity, often resulting in suboptimal clock speed and increased power consumption, especially when trying to accommodate worst-case delays across different logic paths.
Innovation Solution
The implementation of a programmable integrated circuit with multiple clock distribution networks and adjustable delay circuits, allowing for intelligent placement of clock sources and routing to create desired clock skews, thereby optimizing circuit performance by borrowing time from faster paths to support slower paths without reducing overall clock speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional flip-flop-based sequential logic circuits are used with regular clock distribution, then ease of circuit design is improved, but circuit performance is limited due to clock speed being slowed to accommodate worst-case delays
Solution Approach 1:
The patent segments the clock distribution system into multiple independent clock networks (first clock distribution network and second clock distribution network), each serving different regions or types of logic circuits. This segmentation allows different clock frequencies and skew configurations to be applied to different segments, enabling fast logic paths to operate at higher speeds while slow logic paths receive appropriate timing accommodation without limiting the entire circuit's clock speed.
Solution Approach 2:
The patent applies local quality by providing different clock skew characteristics to different regions of the circuit. Fast logic paths receive clocks with minimal or negative skew, while slow logic paths receive clocks with positive skew to accommodate their longer propagation delays. This localized optimization allows each region to operate at its optimal speed rather than being constrained by the worst-case path.
2Speed
If conventional time borrowing schemes with limited delays are used, then some performance improvement is achieved, but optimal performance cannot be obtained due to limited number of delays available
Solution Approach 1:
The patent implements dynamic clock skew adjustment by making the clock distribution networks programmable and configurable. The system can dynamically adjust the amount of skew and select which logic circuits receive clocks from which network based on timing requirements. This dynamic adaptability allows the system to optimize performance for different operating conditions and circuit configurations rather than being fixed to predetermined delay values.
Solution Approach 2:
The patent changes the clock skew parameter to optimize circuit performance. By varying the skew value (the time difference between clock edges arriving at different flip-flops), the system can accommodate different logic path delays. The ability to program and adjust this parameter allows optimal performance to be achieved for various circuit configurations and operating conditions.
3Adaptability or versatility
If multiple clock distribution networks with different types are implemented, then clock skew flexibility is improved for optimizing performance, but device complexity increases
Solution Approach 1:
The patent achieves multi-functionality by designing clock distribution networks that can serve multiple purposes. The same clock network infrastructure is used to provide both global clocking and localized skew-adjusted clocking. The system can configure the networks to serve different functions depending on the timing requirements, reducing the need for entirely separate clock distribution systems for different purposes.
Solution Approach 2:
The patent uses a hierarchical clock distribution approach where a master clock network is copied or replicated into multiple regional networks. These copied networks inherit the basic clock signal but can be independently configured with different skew values and timing characteristics. This copying strategy allows the benefits of multiple specialized networks without duplicating the entire clock generation infrastructure.
4Reliability
If clock sources are intelligently placed and routed to create desired clock skews, then timing reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-configuring the clock distribution network topology and skew values during the design and fabrication process. The intelligent placement of clock sources and the routing configuration are determined in advance based on the circuit's timing requirements. This preliminary configuration ensures timing reliability is built into the hardware structure itself, rather than requiring complex runtime adjustments or calibration procedures that would complicate manufacturing.
Data Source
AI summary
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.