Variable-Length Clock Stretcher for Supply-Voltage Timing Stability
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Solution Overview
Problem
Conventional clock stretchers face challenges in handling rapidly varying supply voltages, leading to timing violations and functional failures due to their reliance on clean power supplies and limited bandwidth in analog delay-locked loops, which are costly and power-intensive, especially in systems with variable load like AI processors.
Innovation Solution
A clock stretcher module that senses supply voltage conditions and adjusts the clock frequency by skipping input clock pulses and repositioning remaining pulses using a delay-locked loop and combiner circuit, operating without intervening voltage regulation, thereby maintaining system stability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog delay-locked loop is used to stabilize clock frequency against supply voltage variations, then the clock stability is improved, but the power consumption and cost increase significantly
Solution Approach 1:
The patent replaces the analog delay-locked loop (a continuous, high-power system) with a digital delay-locked loop that operates in discrete time steps. This substitution uses digital logic and counters instead of analog circuitry, dramatically reducing power consumption while maintaining the ability to stabilize clock frequency against supply voltage variations.
Solution Approach 2:
The patent changes the operating parameters of the delay-locked loop by implementing it in digital domain with discrete time steps rather than continuous operation. This parameter change allows the system to achieve similar stabilization function with much lower power consumption, as digital circuits can be put into low-power states between operations.
2Manufacturing precision
If the delay line resolution is increased to improve clock frequency accuracy, then the manufacturing precision is improved, but the power consumption and die area increase
Solution Approach 1:
The patent resolves the contradiction by moving from an analog continuous delay line to a digital discrete-time system. Instead of increasing resolution within the same analog domain (which would require more physical components and area), the system uses digital counting and timing in a different dimension (discrete time steps), achieving high precision without proportional increases in die area.
Solution Approach 2:
The patent uses a digital counter to track and measure time intervals, creating a digital representation of the delay measurements. This digital copy allows for high-precision frequency stabilization through software or logic-based processing rather than requiring high-resolution analog components, thereby reducing die area.
3Ease of operation
If a digital delay-locked loop is used to eliminate the need for clean power supply, then the ease of operation is improved, but timing violations may occur due to discrete time step adjustments
Solution Approach 1:
The patent implements preliminary action by using a bypass mechanism that can directly pass the input clock to the output when the digital DLL is making adjustments. This preliminary preparation of an alternative signal path prevents timing violations during the discrete adjustment steps, as the system can switch to the bypass path temporarily and then return to the DLL-adjusted path when stable.
Solution Approach 2:
The patent introduces a bypass circuit as an intermediary element between the input and output clocks. This intermediary provides a clean, uninterrupted clock path that mediates between the need for DLL adjustments and the requirement for continuous, violation-free clock output, allowing the system to maintain timing accuracy while operating from unregulated power.
Data Source
AI summary
A clock stretcher includes a delay line, a control unit, and a combiner. The delay line outputs a series of delayed phases of an input clock. The control circuit is clocked by the input clock. It outputs a series of delayed phase enable signals. The combiner circuit receives the delayed phases from the delay line and the delayed phase enable signals from the control circuit, and outputs a modified clock. The control circuit determines if stretching has started, if wraparound must occur, and if a next phase must be enabled. The combiner retimes a delayed phase enable signal for a first delayed phase using a flipflop clocked by a second delayed phase to generate a retimed phase enable signal. The combiner uses the retimed phase enable signal to pass a pulse of the first delayed phase to the output as a pulse of the modified clock.