Clock Signal Switching Circuit for Stable Fast Startup
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Solution Overview
Problem
Fluctuations in the frequency of clock signals during the initialization of electronic circuits can cause errors, and waiting for stabilization results in a loss of time during startup.
Innovation Solution
A system comprising a first electronic circuit generating a clock signal and a stability indicator, and a second electronic circuit that adjusts the clock signal frequency using a frequency divider and multiplexer based on the stability indicator, ensuring the output clock signal stabilizes quickly without exceeding a target frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the clock signal frequency is used directly during initialization, then the startup time is reduced, but the frequency fluctuations cause errors in electronic circuits
Solution Approach 1:
The system dynamically adjusts the clock signal frequency based on the stability indicator state. During initialization, when the stability indicator is in the first state, the frequency is divided by a first factor to ensure stability. When the stability indicator transitions to the second state, the system switches to a second factor (or no division) to maximize performance. This dynamic adjustment resolves the contradiction by adapting the frequency division ratio to the real-time stability condition.
Solution Approach 2:
The invention changes the frequency parameter of the clock signal based on the stability indicator state. By modifying the frequency division factor from the first factor during initialization to the second factor after stabilization, the system optimizes both startup time and operational reliability. This parameter change allows the circuit to operate safely during initialization while achieving maximum performance after stabilization.
2Reliability
If the clock signal frequency is divided by a large factor during initialization, then the risk of errors is reduced, but the effective operating frequency is lowered
Solution Approach 1:
The system transitions from a static frequency division approach to a dynamic one. The frequency division factor is not fixed but changes based on the stability indicator state. This allows the system to use a first division factor during initialization for stability, then switch to a second division factor (or bypass division) after stabilization to maximize operating frequency and productivity.
Solution Approach 2:
The system performs preliminary frequency division during the initialization phase to ensure stable operation before full-speed operations begin. The stability indicator detects when this preliminary stabilization phase is complete, triggering the transition to higher performance mode. This preliminary action ensures reliability is established before maximizing productivity.
Data Source
Figure 1A~1B
Figure 1C
Figure 2
AI summary
The present description relates to an electronic device (100), comprising: - a first electronic circuit (104) configured to generate a first clock signal (CK) and a second signal (READY) indicating a stability state of the frequency of the first signal, the second signal having a first value during a first period and a second value after the first period; and - a second electronic circuit (106) configured to generate an output clock signal (CK_SOC) having a frequency equal to the frequency of the first signal (CK) divided by a first factor (k) when the second signal (READY) is at the first value and having the frequency of the first signal (CK), or a frequency equal to the frequency of the first signal (CK) divided by a second factor (N) lower than the first factor, following a change of the second signal (READY) towards the second value.