Clock Signal Switching Circuit for Low-Power Multi-Phase Memory Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-phase clock circuits in memory devices continue to consume power when in power-off mode due to clock path circuits with power-consuming components, leading to unnecessary power consumption.
Innovation Solution
A clock signal generation circuit that includes a receiver, oscillator, multiplexer, and control circuit to selectively output an oscillator signal to the analog clock generator when it's idle or in power-off mode, bypassing the power-consuming clock path circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock path circuit continuously transmits clock signals to the analog clock generator in power-off mode, then the analog clock generator can return to normal mode and operate normally, but the power consumption of the clock signal generation circuit increases significantly
Solution Approach 1:
The patent implements dynamic switching between different clock signal sources (clock path circuit and oscillator circuit) based on the operational state of the analog clock generator. The control circuit dynamically selects which circuit to activate, making the system adaptive to different modes rather than operating in a fixed continuous manner.
Solution Approach 2:
The patent extracts the essential function of generating clock signals from the clock path circuit and assigns it to a separate oscillator circuit. This allows the clock path circuit to be deactivated in power-off mode while the oscillator circuit independently provides the necessary clock signals, separating the continuous transmission requirement from the power-consuming path.
2Reliability
If the clock path circuit includes power-consuming components like buffers to ensure proper signal transmission, then the clock signals can be reliably transmitted, but the overall power consumption of the system increases
Solution Approach 1:
The patent employs an oscillator circuit that can generate clock signals on-demand without requiring the continuous operation of power-consuming buffer components. The oscillator circuit activates only when needed, replacing the continuous power consumption of buffers with intermittent, lower-power signal generation.
Solution Approach 2:
The oscillator circuit is designed to perform multiple functions: it can provide clock signals during normal operation, during power-off mode recovery, and in place of the clock path circuit when power consumption needs to be reduced. This multi-functionality eliminates the need for dedicated power-consuming components in the clock path.
Data Source
AI summary
A clock signal generation circuit and a clock signal generation method thereof are provided. When an analog clock signal generator circuit does not provide an output clock signal, a control circuit controls a multiplexer circuit to selectively output an oscillator signal provided by an oscillator circuit to the analog clock signal generator circuit, and controls a clock path circuit to stop transmitting an input clock signal.