Clock Synchronization Circuit With Adaptive DLL Update Timing
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Solution Overview
Problem
In semiconductor apparatuses, the difference in delay times between clock signal and data paths prevents accurate phase synchronization, necessitating the use of a data strobe signal for data transmission, which complicates synchronization processes.
Innovation Solution
A synchronization circuit with a variable delay unit, phase difference detection, and a control unit that adjusts delay times and update periods to synchronize the clock signal with the external clock signal, ensuring phase alignment and efficient data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay locked loop (DLL) is used to synchronize the data strobe signal with the external clock signal, then phase synchronization is achieved, but the delay locking time is prolonged
Solution Approach 1:
The synchronization circuit is divided into two independent paths: a first path that detects phase difference between the first clock signal and third clock signal, and a second path that detects phase difference between the first clock signal and fourth clock signal. Each path operates with different update periods, allowing parallel processing of synchronization tasks and reducing overall locking time while maintaining accuracy.
Solution Approach 2:
The update period of the delay control signal is dynamically adjusted based on synchronization status. When the first clock signal and third clock signal have substantially the same phase, the update period is increased (slower updates). When they differ, the update period is decreased (faster updates). This dynamic adjustment accelerates the initial locking process while maintaining stability during operation.
2Speed
If the delay time update period is kept short to reduce delay locking time, then synchronization speed is improved, but power consumption and system complexity increase
Solution Approach 1:
The circuit uses periodic phase difference detection with varying update periods. The first path operates continuously with a first update period, while the second path operates with a second update period that is longer than the first. This periodic action with differentiated periods achieves fast synchronization without requiring continuously high-speed updates, reducing power consumption and complexity.
Solution Approach 2:
The control unit receives phase difference detection signals from both paths and uses this feedback to dynamically adjust the delay control signal. The feedback mechanism allows the system to automatically adapt the update period based on synchronization progress, achieving fast locking without manual intervention or complex external control logic.
Data Source
AI summary
A synchronization circuit may include: a variable delay unit configured to delay a first clock signal by a first delay time set in response to a delay control signal and generate a second clock signal; a first path configured to detect a phase difference between the first clock signal and a third clock signal generated by delaying the second clock signal by a second delay time and generate a phase difference detection signal; a second path configured to generate a second phase difference detection signal in response to a phase difference between the first clock signal and a fourth clock signal; and a control unit configured to generate the delay control signal in response to the phase difference detection signal and vary an update period of the delay control signal in response to the second phase difference detection signal.