Clock Synchronization via Dynamic Jitter Buffer Read Rate Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing systems face challenges in synchronizing data transfer between devices due to clock drift, leading to data loss and artifacts, as they often compensate by deleting large blocks of information, which can result in catastrophic events.
Innovation Solution
A system that includes a capture device, a synchronizer, and a read controller to detect underflow or overflow conditions, compensating for clock drift by adjusting data block sizes and using a monitor to calculate a compensation factor, allowing for fine-resolution synchronization without significant data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large blocks of information are deleted to compensate for clock skews, then clock synchronization is improved, but data loss increases and artifacts are introduced into data streams
Solution Approach 1:
The patent divides the data stream into individual samples rather than processing large blocks. The jitter buffer processes samples one at a time, allowing for fine-grained compensation of clock drift without deleting large portions of data. This segmentation enables precise timing adjustment while preserving data integrity.
Solution Approach 2:
The system dynamically adjusts the buffer fill level parameter to compensate for clock drift. By monitoring the buffer level and modifying the read rate accordingly, the system can correct timing skews continuously without resorting to large-scale data deletion. This parameter-based approach maintains synchronization while preserving data.
2Adaptability or versatility
If separate clocks are used to communicate between devices, then device independence is improved, but clock drift occurs leading to data processing mismatches
Solution Approach 1:
The patent implements a feedback mechanism where the buffer level is continuously monitored and used to adjust the read rate. This closed-loop control compensates for clock drift between independent devices by dynamically adapting the data extraction rate based on actual buffer conditions, maintaining synchronization despite using separate clocks.
Solution Approach 2:
The system transitions from static block-based processing to dynamic sample-by-sample processing. The jitter buffer continuously adapts its behavior based on real-time clock drift conditions, allowing independent devices to maintain synchronization through flexible, dynamic adjustment rather than rigid fixed-rate processing.
3Ease of operation
If data is processed in fixed block sizes, then processing simplicity is improved, but clock drift compensation becomes coarse and disrupts data streams
Solution Approach 1:
The patent segments data processing from fixed blocks to individual samples. This allows the system to maintain simple processing logic while achieving fine-grained synchronization control. Each sample can be independently timed and buffered, providing precise clock drift compensation without complex block manipulation.
Data Source
AI summary
A system synchronizes data flow between a first device and a second device. The system includes a data link that connects two or more devices that are capable of sending and receiving data through a bus. A capture device senses and transfer information through the bus. A ring buffer temporarily stores data transmitted through the bus. A read controller copies or reconstructs data in a length that is different from the length of the data received. A monitor detects underflow or overflow conditions into or out of the ring buffer and compensates for clock drift.