Clock Synchronization Circuit for GALS Sub-Cycle Offset Alignment
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Solution Overview
Problem
In globally asynchronous locally synchronous (GALS) systems, synchronizing clock signals between different subsystems is challenging due to asynchronous operation, leading to communication issues and potential metastable states during signal transmission.
Innovation Solution
A clock synchronization circuit is introduced, which determines the sub-cycle offset between two clock signals and selects rising/falling edges based on this offset to enable communication between clock domains. This circuit includes a sub-cycle offset determination unit and a clock control unit, utilizing a ring oscillator and controller to propagate signals and determine inversion delays, and is integrated with transmitting and receiving circuits to synchronize signals across domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous operation is used in different subsystems, then system flexibility and independence are improved, but communication reliability and synchronization between subsystems deteriorate
Solution Approach 1:
A clock synchronization circuit is introduced as an intermediary component between asynchronous subsystems. The circuit includes a first clock domain synchronized to a first clock signal and a second clock domain synchronized to a second clock signal, with interface circuits that use handshake signals to mediate communication. This intermediary structure allows independent subsystems to communicate reliably without requiring global clock synchronization.
Solution Approach 2:
The system is divided into separate clock domains, each with its own independent clock signal and synchronized circuits. By segmenting the system into isolated clock domains with defined interface protocols, each subsystem maintains independence while communication between domains is managed through controlled handshake mechanisms, resolving the contradiction between flexibility and reliability.
2Reliability
If clock signals are synchronized between subsystems, then communication reliability is improved, but system complexity and synchronization overhead increase
Solution Approach 1:
Synchronization is applied locally within each clock domain rather than globally across the entire system. Each subsystem maintains its own clock synchronization independently, and only interface circuits between domains require coordination through handshake signals. This local approach reduces overall system complexity while maintaining communication reliability.
Solution Approach 2:
Handshake signals provide feedback mechanisms between clock domains, allowing receiving circuits to notify transmitting circuits about data readiness and status. This feedback enables reliable communication without requiring complex continuous synchronization, as the handshake protocol manages timing coordination on-demand based on actual data transmission needs.
3Measurement precision
If handshake signals are used for interface communication, then data transmission accuracy is improved, but communication time and latency increase
Solution Approach 1:
The handshake mechanism operates in periodic cycles: data becomes ready, receiving circuit detects readiness, handshake signal is asserted, data is sampled, and acknowledgment is returned. This structured periodic action ensures accurate data capture at defined intervals while minimizing idle waiting time, balancing precision with efficiency.
Data Source
AI summary
Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.