Clock Synthesis Circuitry for SHB-Synced Display Refresh
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Solution Overview
Problem
Existing PLL designs for LED driver circuits in digital signage and display applications are complex, costly, and often unsynchronized with vertical sync signals, leading to visual artifacts due to PVT variations, which result in partial refreshes and inefficiencies in clock-driven processing.
Innovation Solution
A clock synthesis circuit using a ring oscillator, divide-by-M circuitry, and counter mechanisms to generate a precise number of output clock pulses synchronized with system heartbeat pulses, incorporating clock shaping and spread spectrum techniques to reduce electromagnetic interference and align with SHB timing, thereby mitigating visual artifacts and silicon real estate usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL design is used for clock generation in LED driver circuits, then clock frequency control is achieved, but the circuit complexity increases and synchronization with vertical sync signals is lost due to PVT variations
Solution Approach 1:
The patent replaces the analog PLL mechanism with a digital counter-based clock synthesis system. Instead of using phase detectors, loop filters, and voltage-controlled oscillators, the invention uses digital counters that divide system heartbeat pulses to generate precise clock frequencies. This substitution eliminates analog component variations and achieves exact synchronization with vertical sync signals while reducing circuit complexity.
Solution Approach 2:
The patent changes the fundamental operating parameter from analog voltage control to digital pulse counting. By using integer division ratios of the system heartbeat frequency, the system achieves precise clock frequency control without the drift and synchronization issues inherent in analog PLL designs. The counter-based approach allows exact integer divisions that remain stable across PVT variations.
2Power
If traditional PLL components are used, then frequency control is possible, but silicon real estate is excessively consumed
Solution Approach 1:
The patent extracts and removes the bulky analog components (phase detector, loop filter, VCO) from the clock generation system, retaining only the essential frequency control function through digital counters. This extraction eliminates unnecessary circuitry that consumes silicon real estate while preserving the core capability of generating controlled clock frequencies for LED driver operation.
Solution Approach 2:
The patent uses a simplified digital copy of the frequency control function instead of the full analog PLL implementation. By implementing clock synthesis through counter circuits that replicate the frequency division functionality, the system achieves the same control capability with dramatically reduced silicon area, as digital counters require far fewer transistors than their analog counterparts.
3Stability of the object's composition
If analog loop filter components are used in PLL, then phase error filtering is achieved, but the device size and cost increase
Solution Approach 1:
The patent substitutes the analog loop filter with a digital filtering approach implemented through counter circuits. Instead of using resistors, capacitors, and operational amplifiers to filter phase errors, the system uses digital counting and averaging techniques that inherently provide stability while being much easier to manufacture with standard digital CMOS processes. The counter-based approach eliminates analog component tolerances and drift issues.
Data Source
AI summary
A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply “clocks”) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.