Clock Tree Back-Gate Biasing With Local Reference Generation
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Solution Overview
Problem
High-speed clock distribution trees in high-speed interfaces are significant power contributors, and existing methods for back-gate biasing in Fully Depleted Silicon On Insulator (FD-SOI) transistors either result in high power consumption or increased area, failing to optimize both power and area effectively.
Innovation Solution
A local reference generator is introduced to drive the back gates of clock buffers, allowing for programmable threshold voltage control via back-gate biasing, which optimizes speed and power consumption while minimizing area by sharing wells among transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fully inverted wells are used for back-gate biasing in clock buffers, then area is reduced by sharing common wells, but power consumption increases
Solution Approach 1:
The patent applies different back-gate biasing strategies to different regions of the clock distribution network. Specifically, buffers closer to the clock source use fully inverted wells for area efficiency, while buffers farther away use separate wells for power optimization. This local differentiation resolves the contradiction by allowing each region to prioritize the parameter most critical to its function.
Solution Approach 2:
The patent introduces dynamically controllable back-gate biasing voltages that can be adjusted based on operating conditions. By making the biasing scheme dynamic rather than fixed, the system can adapt between area-optimized and power-optimized configurations, resolving the static contradiction between these two parameters.
2Use of energy by stationary object
If separate wells are used for each transistor back gate, then power consumption is reduced, but area increases
Solution Approach 1:
The patent segments the clock distribution network into multiple zones with different back-gate biasing configurations. By dividing the network into segments that can use different strategies (shared wells vs. separate wells), the system achieves both area efficiency in some regions and power efficiency in others, resolving the contradiction through spatial segmentation.
Solution Approach 2:
Different quality requirements are applied to different parts of the clock tree. The patent allows buffers in power-critical regions to use separate wells for lower power consumption, while buffers in area-critical regions use shared wells, thus resolving the contradiction through localized quality differentiation.
3Productivity
If back-gate biasing is applied to control threshold voltage, then speed and power are optimized, but device complexity increases
Solution Approach 1:
The patent implements a universal back-gate biasing control mechanism that serves multiple functions: threshold voltage control, power optimization, and speed enhancement. By making the biasing system multi-functional, the added complexity is justified by the simultaneous achievement of multiple performance goals, resolving the contradiction between productivity improvement and device complexity.
Data Source
AI summary
The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.