Dynamic Clock Tree Planning with Feedthrough-Aware Timing
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Solution Overview
Problem
Conventional clock tree planning systems do not adequately consider the number of feedthroughs in clock tree topologies, leading to suboptimal circuit designs that may compromise existing layouts or require undesirable changes.
Innovation Solution
Implementing a feed-timing cost parameter as a vector of path-length and encountered feedthroughs count to generate multiple clock tree topologies, allowing users to balance timing and feedthroughs, presented through a graphical interface for selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional clock tree planning systems are used, then the design process is simpler, but the feedthrough count is not optimized and circuit layouts may be compromised
Solution Approach 1:
The system changes the parameter of feedthrough count consideration from being ignored to being a key optimization parameter. By incorporating feedthrough count as a specific metric in clock tree planning, the system generates topologies that respect block boundaries and maintain layout integrity without excessive feedthroughs.
Solution Approach 2:
The system dynamically adjusts the optimization criteria by allowing users to specify different feedthrough count thresholds and priorities. The clock tree planning process adapts to different design requirements by modifying its cost function and search parameters based on user input, making the planning both layout-aware and flexible.
2Adaptability or versatility
If multiple clock tree topologies are generated with different feedthrough counts, then design flexibility is improved, but processing resources and computational time increase
Solution Approach 1:
The system segments the clock tree planning process into multiple iterations, each generating topologies with different feedthrough count constraints. By dividing the optimization into discrete steps with varying parameters, the system provides designers with a portfolio of options ranging from timing-optimized to feedthrough-optimized solutions, enabling flexible selection without requiring exhaustive search of all possible topologies.
Solution Approach 2:
The system varies key parameters (feedthrough count thresholds, cost function weights) across different planning iterations to generate diverse topology options. This parameter variation approach allows the system to explore the solution space efficiently by focusing on specific regions of interest rather than exhaustively searching all possibilities, thus balancing design flexibility with processing efficiency.
3Stability of the object's composition
If feedthrough count is reduced, then block boundary integrity is improved, but clock path length may increase
Solution Approach 1:
The system dynamically balances two competing objectives by allowing users to adjust the relative importance of feedthrough count versus clock path length through configurable parameters. The planning algorithm adapts its search strategy based on user-specified priorities, generating topologies that achieve the desired balance between maintaining block boundary integrity and minimizing clock distribution delay.
Data Source
AI summary
A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.