Clocked Comparator DFE Circuit With Series Transistor Isolation
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Solution Overview
Problem
Existing decision feedback equalizers face challenges in reducing intersymbol interference due to increased parasitic capacitances when implementing parallel differential pairs, which slows down data transfer rates.
Innovation Solution
The use of series transistors to isolate signal paths from parasitic capacitances of feedback differential pairs, reducing capacitive loading and allowing higher data rates by coupling series transistors with input differential pair transistors and configuring gates to receive decision feedback signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel differential pairs are used to implement decision feedback equalization, then intersymbol interference reduction is improved, but parasitic capacitances increase which slows down data transfer rates
Solution Approach 1:
The patent segments the feedback path by introducing series transistors (third and fourth transistors) between the parallel differential pairs and the feedback nodes. This segmentation isolates the signal paths from parasitic capacitances while maintaining the equalization function, thereby resolving the contradiction between interference reduction and speed.
Solution Approach 2:
The series transistors act as intermediaries that couple the parallel differential pairs to the feedback nodes. These intermediary elements transfer the equalization signal while blocking the propagation of parasitic capacitances, thus improving data transfer rate without sacrificing intersymbol interference reduction.
2Speed
If series transistors are introduced to isolate signal paths from parasitic capacitances, then capacitive loading is reduced and data rates increase, but device complexity increases
Solution Approach 1:
The patent merges the series transistors into the existing parallel differential pair structure, integrating the isolation function within the comparator circuit itself. This merging approach reduces device complexity by eliminating separate isolation stages while maintaining the speed improvement through capacitive loading reduction.
Data Source
AI summary
An input stage of a comparator includes a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage, a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage, a third transistor coupled in series with the first transistor, and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage further includes a sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.