Transmitter/Receiver Shaping Networks TRIZ Cases

An internal common mode signal replaces extra alignment circuitry, enabling AC-coupled high-speed receivers with lower power use.

Blocks abnormal HDMI DC5V input caused by reflection or resonance, passing only in-range voltage to protect the receiving LSI.

A transmit-path filter and separate antenna feeds suppress passive intermodulation distortion, protecting receiver sensitivity in multi-band RF systems.

A passive resistor network sums ODVS inputs and shunts coupled transmit interference to improve dynamic range, common mode rejection, and ESD protection.

Independent low- and high-frequency current paths improve CTLE gain programmability, reduce parasitic effects, and lower power use.

A slight clock-sampling offset lets a PAM receiver adapt equalizer coefficients accurately and recover the channel inverse response.

Temperature and supply correction currents stabilize DFE bias voltages against PVT drift, reducing memory data errors.

A replica amplifier and op-amp bias loop hold differential amplifier gain stable across temperature without adding input load.

Capacitive feedback at the sample-hold node cuts DFE loop latency, sense-amplifier count, and power in high-speed receivers.

Parallel filters and a nonlinear combiner equalize digital input signals while avoiding cross-terms to cut power, area, and complexity.

Series transistors isolate comparator signal paths from DFE parasitic capacitance, reducing loading and supporting higher data rates.

Earlier second-clock timing stabilizes tap2 correction data in a decision feedback equalizer, improving ISI removal accuracy.

Current-variation detection sets transistor off-timing in PWM node links to cut EMI noise while keeping onboard communication stable.

Switching ARINC-429 data rates through encoded signal sequences removes extra slew-rate control pins, cutting hardware cost and complexity.

A common-mode dither and correlation loop adjusts terminal capacitance to cut mode conversion and preserve differential signal quality.

Multiple training runs detect unstable DFE tap settings, then switch receiver equalization state to cut bit errors and preserve eye margin.

Adaptive equalizer updates in a PAM receiver recover inverse channel response under asynchronous sampling and long-channel distortion.

Time-interleaved sampling and discrete-time gain replace hard-to-linearize continuous-time amplification in high-rate serial receivers.

Frame-based static gain compensation helps DPD feedback correct power amplifier nonlinearity, cutting bit errors and spectrum spurs.

Analog FFE and interleaved DFE split PAM signal equalization to sustain high bit rates under lower signal-to-noise conditions.

Precisely timed pre-emphasis in pull-up and pull-down drivers compensates channel loss while avoiding distortion in high-speed data links.

Closed-loop bias control and active inductors help a CTLE keep high-frequency gain while cutting layout area and common-mode noise sensitivity.

A feedback-driven DPD scheme compares amplitude and phase errors after amplification to cut bit errors and out-of-band spurs.

A passive RLC buffer with feedback-controlled current sources shifts DC level for CTLE inputs while cutting buffer power in wideband links.

Extra FFE and DFE taps target deterministic track-and-hold ISI in TI-ADCs, improving link quality with lower analog overhead.

Additional driver simulations damp dominant-to-recessive bus transitions, cutting oscillation time for higher CAN and CAN FD bit rates.

A brief short circuit during dominant-to-recessive CAN transitions damps oscillation, enabling higher bit rates with reliable signal recognition.

Embedding receiver IDs in frozen bits lets DCI blind detection stop early on non-matching candidates, reducing latency, energy use, and false alarms.

Offset-shifted CTLE and odd-even DFE stages capture multiple eye-openings to cut ISI-driven bit error loss in high-speed receivers.

Dynamic AD discrimination level control and transfer correction improve digital receiver resolution under low-SNR, high-dispersion optical signals.

Cycle-by-cycle software delay modulation spreads EMI from fixed-frequency sampling without extra SSCG hardware, cutting sensor-system interference.

Separate UE and cell ID scrambling masks in DCI frozen and information bits enable early decode termination, lower false alarms, and cut blind detection load.

Multi-level transition signaling raises serial link capacity without higher clock rates, helping reduce erroneous operation at high frequencies.

Software-modulated time delays spread EMI in fixed-sampling sensor systems, cutting interference without extra hardware or SSCG complexity.

A switch-and-resistor path briefly links CANH and CANL during transmitter state changes to suppress ringing and stabilize bus voltage.

Multiple low-frequency transmission lanes are serialized to raise link capacity while reducing erroneous operation at high clock frequencies.

A dual-path CTLE combines DC gain recovery and high-frequency boost in one stage to improve signal integrity with less power and silicon area.

Selectable TIA feedback and fixed DFE tap weights let an ONU reach up to 10 Gbps with 2.5 Gbps components, avoiding hardware swaps.

Phase compensation capacitors and an inductor reduce bypass-to-attenuation path mismatch, keeping RF attenuation steps low in phase shift.

DAC-controlled resistor and capacitor modules on transformer secondary windings tune CML peaking magnitude without shifting frequency.

Two pre-distortion paths and feedback-generated parameters compensate amplifier memory effects and carrier aggregation distortion.

Asynchronous sampling in CTLE isolation mode corrects sense amplifier offset without multiplexers, preserving bandwidth and lowering power.

Continuous-time delay cells with adaptive feed-forward equalization correct ISI while avoiding bulky inductors, reducing jitter and chip area.

Switchable resistor-capacitor equalization on transformer secondary windings tunes CML peaking magnitude without frequency shift or high power.

Asynchronous sampling in CTLE isolation mode corrects SERDES sense amplifier offset without extra multiplexers, saving area and power.

Multi-phase sampling and time borrowing cut feedback delay in a partial response equalizer, enabling higher data rates with less ISI.

Direct oversampled LUT pulse shaping lowers DSSS baseband PAR, cuts PA power use, and preserves IEEE spectral mask and EVM compliance.

Secondary-winding equalization lets CML outputs tune peaking magnitude without shifting frequency, improving bandwidth and channel reliability.

Separating phased low-frequency signals, then up- and down-converting them, cuts mixer count, noise, and power use in RF reception.

Bits are encoded with different wave periods instead of duty ratios, simplifying receiver detection while maintaining reliable data transmission.

Segmented equalizer stages cancel inter-symbol interference while disabling unused components to lower power consumption during PAM-4 signaling.

Pre-adjusting amplifier gain handles short pulses and multipath reflections without dynamic control complexity.

A passive equalization circuit uses an inductor network to distribute capacitive load between transmitter and receiver.