Multi-Phase Partial Response Equalizer for High-Rate ISI Mitigation
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Solution Overview
Problem
Conventional partial response equalizers face challenges in maintaining signal quality due to dispersion-type inter-symbol interference (ISI) at higher signaling rates, which limits their ability to operate effectively at increased clock rates.
Innovation Solution
The implementation of a multi-data rate partial response equalizer that employs a time borrowing technique, allowing for reduced timing constraints by increasing the time for signal propagation between sampled bits without altering the clock signal periods, enabling the circuit to function at higher data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional partial response equalizer designs are used, then the circuit can operate at standard clock rates, but the longest feedback path delay imposes a lower limit on unit interval that prevents operation at higher data rates
Solution Approach 1:
The feedback path is segmented into two separate paths: a first feedback path that feeds back a first sampled bit to a first multiplexer, and a second feedback path that feeds back a second sampled bit to a second multiplexer. This segmentation allows each path to have reduced delay requirements, enabling operation at higher data rates while maintaining the necessary feedback functionality.
2Productivity
If the clock rate is increased to achieve higher data rates, then productivity improves, but the dispersion-type inter-symbol interference becomes more pronounced and degrades signal quality
Solution Approach 1:
The equalizer performs preliminary equalization processing on the incoming data signal by comparing each bit to multiple threshold levels and selecting appropriate sampled bits based on previously received bits. This preliminary action mitigates dispersion-type ISI before the signal is further processed, enabling reliable operation at higher data rates where ISI would otherwise be more pronounced.
3Productivity
If parallel sampling paths are used, then two bits can be sampled per clock period, but the longest feedback path delay still imposes timing constraints that limit clock rate increases
Solution Approach 1:
The parallel sampling architecture is enhanced by segmenting the feedback paths associated with each sampling path. Each sampled bit has its own dedicated feedback path to the corresponding multiplexer, allowing the feedback delay to be reduced and decoupled from the clock period constraints, thereby enabling higher clock rates while maintaining parallel sampling efficiency.
Data Source
AI summary
A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.