Time-Interleaved Serial Receiver for High-Rate Linear Amplification
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Solution Overview
Problem
Achieving linearity in analog amplifiers is challenging, particularly at high data rates, limiting the speed performance of wired communication receivers.
Innovation Solution
A serial receiver design combining continuous-time equalization, time-interleaving, and discrete-time variable-gain amplifiers to ensure linear amplification of high-speed signals, reducing the need for continuous-time amplification and operating within more linear voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If continuous-time amplification is used to achieve high data rate reception, then the receiver can handle high symbol rates, but linearity becomes difficult to obtain and performance is limited
Solution Approach 1:
The patent divides the continuous-time amplification function into multiple discrete-time amplifiers operating in parallel. Each discrete-time amplifier processes a portion of the sampled signal with controlled gain, avoiding the linearity issues of continuous-time amplification while maintaining high data rate capability through parallel processing
Solution Approach 2:
The patent replaces the continuous-time analog amplification mechanism with a discrete-time digital signal processing approach. By converting the continuous signal to discrete samples and applying digital gain control, the system achieves high precision linearity that is difficult to obtain in continuous-time analog systems
2Power
If continuous-time amplification is used, then signal amplification is achieved, but the amplifier operates outside linear voltage ranges reducing overall linearity
Solution Approach 1:
The patent changes the operating parameters by using discrete-time sampling and digital gain control instead of continuous-time analog amplification. This allows precise control of amplification parameters within linear voltage ranges, achieving both sufficient power amplification and high linearity through digital parameter management
3Manufacturing precision
If discrete-time variable-gain amplifiers are used instead of continuous-time amplifiers, then linearity is improved, but device complexity increases
Solution Approach 1:
The patent segments the amplification function across multiple discrete-time amplifiers that process parallel sample streams. While individual amplifiers are simple, the parallel architecture achieves the required linearity performance without requiring each component to be highly complex
Data Source
AI summary
A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.