TI-ADC Equalizer Taps for Track-and-Hold ISI Cancellation
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Solution Overview
Problem
Integrated circuits with time-interleaved analog-to-digital converters (TI-ADCs) face challenges in mitigating inter-symbol interference (ISI) induced by cascaded track-and-hold circuits, which affects data transmission quality and requires costly analog circuitry adjustments.
Innovation Solution
The implementation of a digital signal processing system (DSP) with a feed forward equalizer (FFE) and/or decision feedback equalizer (DFE) having extra taps and expanded equalization ranges to digitally correct the ISI, allowing for scalable and flexible mitigation of ISI without significant performance loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog circuitry adjustments are used to mitigate ISI, then data transmission quality is improved, but implementation cost and device complexity increase
Solution Approach 1:
The patent replaces analog circuitry adjustments with digital signal processing. Specifically, a digital equalizer with extended taps is used to compensate for ISI instead of modifying analog track-and-hold circuits, thereby reducing device complexity while maintaining transmission quality
Solution Approach 2:
The patent changes the equalization range parameter by extending the digital equalizer taps to cover the N×Mth unit interval. This parameter extension allows the equalizer to address ISI components that were previously beyond its reach, improving transmission quality without adding analog complexity
2Reliability
If digital equalization range is extended to cover N×Mth UI, then ISI mitigation is improved, but implementation overhead increases
Solution Approach 1:
The patent segments the equalization function into distinct tap components, where specific taps are assigned to compensate for ISI at the N×Mth unit interval. This segmentation allows targeted mitigation without requiring a complete redesign of the entire equalization system
Solution Approach 2:
The patent creates a universal digital equalizer structure that can handle multiple ISI components simultaneously. The same equalizer architecture with extended taps mitigates both traditional ISI and the specific N×Mth UI ISI component, reducing overall implementation overhead compared to separate compensation circuits
3Reliability
If FFE and DFE are configured with extra taps, then equalization range is expanded, but power consumption increases
Solution Approach 1:
The patent applies partial action by adding only the specific extra taps needed to cover the N×Mth unit interval rather than uniformly increasing the number of taps across the entire equalization range. This targeted approach expands equalization range while minimizing additional power consumption
Solution Approach 2:
The patent implements dynamic tap configuration where the equalizer adapts its tap structure based on the specific ISI characteristics of the N×Mth unit interval. This dynamic approach allows the system to maintain expanded equalization range while optimizing power consumption by activating only necessary taps
Data Source
AI summary
Apparatus and associated methods relate to targeted digital correction of a predetermined component of inter-symbol interference (ISI) associated with two or more ranks of cascaded track-and-hold (T/H) front-end circuits of a Time-Interleaved analog-to-digital converter (TI-ADC). In an illustrative example, for two T/H circuit ranks of size N and M, the predetermined component to be compensated may be located at (N×M)th unit interval (UI). A feed forward equalizer (FFE) and/or a decision feedback equalizer (DFE) in a digital signal processing system (DSP) may be then configured to have extra taps and corresponding expanded equalization ranges to mitigate the ISI. Thus, a deterministic ISI component at the N×Mth UI may be digitally corrected by providing equalization with N×M taps at low cost to facilitate scaling to higher bit rates.