SerDes Equalizer Circuit for ISI Eye-Opening Capture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-speed digital data transmission systems, such as those using serializer/de-serializer (SerDes) receivers, signal degradation due to limited channel bandwidth leads to inter-symbol interference (ISI), causing errors in received signals, which existing equalization methods struggle to fully address.
Innovation Solution
The implementation of a receiver circuit that includes a voltage shifting amplifier circuit, a continuous time linear equalizer (CTLE), and a decision feedback equalizer (DFE) with odd and even data equalizers, which applies offset voltages to linearly and non-linearly equalize signals, capturing eye-openings to reduce bit error ratio (BER) loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing equalization methods are used, then signal transmission is maintained, but bit error ratio loss occurs due to inter-symbol interference
Solution Approach 1:
The equalizer is divided into multiple independent equalizer units, each responsible for equalizing specific eye-openings (first eye-opening, second eye-opening, third eye-opening). This segmentation allows each unit to specialize in capturing and equalizing particular signal levels, thereby reducing inter-symbol interference and improving bit error ratio performance.
Solution Approach 2:
The equalizer dynamically selects and switches between different equalizer units based on which eye-opening is currently being captured. The system adapts its equalization strategy in real-time by activating the appropriate equalizer unit (first, second, or third) depending on the signal conditions, enabling effective compensation for varying inter-symbol interference patterns.
2Reliability
If multiple equalizer units are implemented to capture different eye-openings, then bit error ratio improves, but device complexity increases
Solution Approach 1:
Multiple equalizer units are designed with identical or similar circuit architectures, allowing them to perform the same equalization function for different eye-openings. This universal design reduces the overall complexity compared to implementing entirely different equalization circuits for each eye-opening, while still achieving improved bit error ratio performance.
Solution Approach 2:
The equalizer implements multiple copies of the same equalization circuitry (first equalizer unit, second equalizer unit, third equalizer unit), each tuned to capture different eye-openings. This copying approach allows the system to achieve multiple equalization functions using replicated hardware blocks, simplifying design and implementation while improving reliability.
Data Source
AI summary
An integrated circuit is disclosed. The integrated circuit includes a first equalizer circuit and a second equalizer circuit. The first equalizer circuit is configured to equalize an input signal which is added by offset voltages that are different from each other, to generate output signals with voltage levels that are different from each other. The second equalizer circuit coupled to the first equalizer circuit. The second equalizer circuit includes a first equalizer unit and a second equalizer unit. The first equalizer unit is configured to equalize the output signals, to generate odd data signals. The second equalizer unit is coupled to the first equalizer unit and configured to equalize the output signals, to generate even data signals. A method is also disclosed herein.