CTLE Active-Load Layout With Common-Mode Noise Immunity

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Solution Overview

Problem

Continuous-time linear equalizers (CTLEs) face challenges in compact layout design and sensitivity to common-mode noise, with inductors occupying large layout areas and finite output impedance causing gain drops in the presence of common-mode noise.

Innovation Solution

A CTLE design incorporating a common-source amplifier, current source, active load, common-mode sensing circuit, current source controller, and active load controller, which uses active inductors and closed-loop bias voltage control to maintain gain insensitivity to common-mode noise and reduce layout area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If inductors are used in the load circuit to increase impedance at high frequency, then high-frequency gain is boosted, but layout area is significantly increased

Engineering Contradiction:
Improvehigh-frequency gainVSAvoidlayout area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent replaces physical inductors with active inductor circuits implemented using MOS transistors. The active inductor uses a MOS transistor with its gate connected to a bias voltage to provide inductive impedance at high frequencies, eliminating the need for large physical inductor components while maintaining the high-frequency gain enhancement.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the impedance characteristics of the load circuit by using active inductors that provide frequency-dependent impedance. The active inductor circuit presents a high impedance at high frequencies (jωL) while occupying minimal layout area, effectively changing the electrical parameters without increasing physical dimensions.

Inventive Principle:
Principle #35Parameter changes

2Power

If current source is used to bias the common-source amplifier, then gain is controlled, but finite output impedance causes gain drop in presence of common-mode noise

Engineering Contradiction:
Improvegain controlVSAvoidimmunity to common-mode noise
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent introduces a common-mode sensing circuit that detects the common-mode voltage at the output and feeds this information back to a control circuit. The control circuit adjusts the bias voltage of the current source in real-time to compensate for common-mode noise effects, maintaining stable gain despite finite output impedance of the current source.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediate control circuit that acts as a mediator between the common-mode sensing circuit and the current source. This control circuit processes the sensed common-mode voltage and generates appropriate bias voltage adjustments, effectively isolating the gain control function from the harmful effects of common-mode noise.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If compact layout is achieved by removing inductors, then area is reduced, but high-frequency gain enhancement is lost

Engineering Contradiction:
Improvelayout areaVSAvoidhigh-frequency gain
Core Design Contradiction:
Area of stationary objectVSPower

Solution Approach 1:

The patent substitutes physical inductors with active inductor implementations using MOS transistors configured to provide inductive impedance. This substitution maintains the high-frequency gain enhancement function while reducing layout area, as the active inductor can be implemented using standard CMOS transistor layouts without requiring large external inductor components.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11381427B1Continuous-time linear equalizer of compact layout and high immunity to common-mode noise
Publication Date: 2022.07.05 REALTEK SEMICON CORP
  • US11381427B1 patent drawing
  • US11381427B1 patent drawing
  • US11381427B1 patent drawing

AI summary

A continuous-time linear equalizer (CTLE) having a common-source amplifier configured to receive an input signal and output an output signal in accordance with a biasing current; a current source controlled by a first bias voltage and configured to output the biasing current; an active load controlled by a second bias voltage and configured to be a load of the common-source amplifier; a common-mode sensing circuit configured to sense a common-mode voltage of the output signal; a current source controller configured to output the first bias voltage in accordance with the common-mode voltage and a reference voltage derived from a supply voltage of the active load and a first reference current; and an active load controller configured to output the second bias voltage in accordance with the supply voltage of the active load and a second reference current.