Clocked Delay Line Frequency Divider for Low Duty Cycle Error
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Solution Overview
Problem
Existing signal processing circuits face challenges in achieving frequency division by an odd number with minimal duty cycle errors, which affects signal processing quality and spurious response suppression in applications like frequency synthesis and harmonic rejection mixing.
Innovation Solution
A signal processing circuit utilizing a clocked delay line with an enable circuit that differentiates between rising and falling edges, introducing additional delays for one type of transition, allowing for precise frequency division by an odd number and minimizing duty cycle errors, thereby enhancing signal processing quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a frequency division by an odd number is performed using conventional circuits, then the frequency division function is achieved, but the duty cycle error increases
Solution Approach 1:
The frequency division function is segmented into multiple sequential stages: a delay line that delays the input signal by one clock cycle, a selection unit that selectively passes through or inverts delay line outputs based on counter state, and a counter that tracks the number of input signal transitions. This segmentation allows precise control over output signal transitions to achieve 50% duty cycle with odd frequency division ratios.
Solution Approach 2:
The circuit employs dynamic elements including a selectable delay line with variable delay periods, a counter that dynamically tracks input signal transitions, and a selection unit that adaptively chooses between different delay line outputs based on the current counter state. This dynamic operation enables the circuit to maintain 50% duty cycle across different odd frequency division ratios.
2Measurement precision
If a frequency division by an odd number is performed, then the frequency synthesis function is achieved, but the phase relationship precision deteriorates
Solution Approach 1:
The circuit uses a counter that counts the number of rising edges in the input signal and provides feedback to the selection unit. This feedback mechanism ensures that the selection unit correctly identifies when to pass through or invert delay line outputs, maintaining precise phase relationships between output signals and achieving accurate 50% duty cycle even with odd frequency division ratios.
Solution Approach 2:
The delay line acts as an intermediary element that introduces a controlled time delay between the input signal and the selection unit. This intermediary delay allows the circuit to synchronize transitions and maintain precise phase relationships, ensuring that output signals have equidistantly spaced transitions despite the odd frequency division ratio.
3Ease of manufacture
If the circuit complexity is reduced, then the manufacturing cost decreases, but the duty cycle error increases
Solution Approach 1:
The delay line serves multiple functions: it delays the input signal by one clock cycle, provides selectable delay outputs for different frequency division ratios, and enables precise transition timing control. This multi-functionality reduces the need for separate dedicated circuits for each function, lowering overall circuit complexity and manufacturing cost while maintaining 50% duty cycle accuracy.
Solution Approach 2:
The circuit changes operational parameters dynamically: the delay line can be selectively configured to provide different delay periods, the counter tracks different numbers of input transitions for different odd frequency division ratios, and the selection unit adapts its selection based on counter state. These parameter changes enable a single circuit to achieve multiple odd frequency division ratios with consistent 50% duty cycle accuracy.
Data Source
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AI summary
A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.