Clocked Digital Input Circuit for High-Voltage Sensor Sampling
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Solution Overview
Problem
Digital input modules in industrial automation face high power consumption due to existing methods like resistor divider and current limiter circuits, limiting channel density and requiring larger power supplies.
Innovation Solution
A digital input circuit with a series connection of a current limiter and an electronic switch, coupled with a logic level shifter and clock, reduces power consumption by turning off current flow when not sampling the input signal, using a clock to control the switch and minimize power use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a resistor divider circuit is used to detect high voltage sensor signals, then the circuit can detect voltage thresholds and provide galvanic isolation, but power consumption increases quadratically with sensor voltage
Solution Approach 1:
The patent applies periodic action by using a clock signal to periodically switch the electronic switch on and off. The current limiter is only active during specific clock cycles when sampling occurs, rather than continuously. This periodic operation dramatically reduces average power consumption while maintaining the ability to detect voltage thresholds through the voltage comparator during active sampling periods.
Solution Approach 2:
The patent implements dynamics by making the current limiter switchable through an electronic switch controlled by a clock signal. The circuit transitions from a static always-on configuration to a dynamic system that activates the current limiter only when needed for sampling. This dynamic control allows the system to maintain measurement precision during active periods while minimizing power consumption during inactive periods.
2Use of energy by moving object
If a current limiter circuit is used to reduce power consumption, then power usage decreases, but channel density is still limited and larger power supplies are required
Solution Approach 1:
By implementing periodic sampling controlled by a clock signal, the system achieves ultra-low power consumption during idle periods. This allows significantly more channels to be packed into the same power budget, thereby increasing channel density. The periodic operation ensures that current is drawn only during brief sampling intervals rather than continuously.
Solution Approach 2:
The patent changes the operational parameters by introducing clock-controlled timing to the current limiter operation. Instead of a fixed current limit, the system dynamically adjusts when current limiting is applied based on sampling requirements. This parameter change enables the system to support higher channel density by reducing the average current draw per channel.
3Reliability
If continuous current flows through divider resistors to maintain detection capability, then voltage threshold detection is maintained, but power consumption increases
Solution Approach 1:
The system uses periodic action by enabling the current limiter and electronic switch only during clock-controlled sampling intervals. During these brief periods, sufficient current flows through the circuit to allow the voltage comparator to accurately detect voltage thresholds. Between sampling intervals, the switch remains open and current flow is minimized, dramatically reducing power consumption while maintaining detection capability when needed.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that during each active sampling period, the circuit is fully operational with current flowing through the divider resistors and comparator. The clock-controlled switching ensures that useful detection action continues uninterrupted during sampling windows, while eliminating wasteful continuous current flow during non-sampling periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by 50% or more, enhancing channel density and reducing the need for larger power supplies in digital input modules.
Implementation Method 1
a logic level shifter including a voltage comparator and a low pass filter
Implementation Method 2
a logic level shifter including a voltage comparator and a low pass filter
Data Source
AI summary
A digital input circuit includes a series connection of a current limiter and a switch having a switch control input coupled between a signal input and ground, and a logic level shifter coupled to the signal input and having a switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output. A digital input method includes coupling an input signal to ground with a current limiter by closing an electronic switch, providing an output signal responsive to the input signal, where a maximum amplitude of the input signal is greater than a maximum amplitude of the output signal, by latching the output signal while the input signal is above a threshold voltage and opening the electronic switch after the output signal is latched.