Clocked Level Shifter Latch for Voltage-Domain Time Borrowing
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Solution Overview
Problem
Traditional circuitry does not allow time borrowing across voltage domains, limiting the ability of level-shifting circuitry to relax edge-to-edge timing requirements and facilitate efficient data transfer between circuits operating at different voltage levels.
Innovation Solution
The implementation of level-shifting circuitry that generates a pulse signal based on an input clock edge, allowing the input to change during the pulse and enabling time borrowing by transparently passing and level shifting the input, with pull and feedback circuitry driving and maintaining the output across voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional level-shifting circuitry is used, then voltage level conversion is achieved, but time borrowing across voltage domains is not allowed
Solution Approach 1:
The patent employs periodic clock signals to control the level-shifting circuitry, enabling time borrowing by synchronizing data transfer with clock cycles. The clocked architecture allows output signals to be valid during specific clock periods, permitting upstream circuits to borrow time for computation while ensuring proper sampling at clock edges.
Solution Approach 2:
The patent introduces clocked latches and control signals as intermediaries between different voltage domains. These intermediary elements buffer and synchronize data transfer across voltage boundaries, enabling time borrowing while maintaining timing integrity through controlled transparency windows during clock cycles.
2Length of moving object
If edge-to-edge timing requirements are enforced, then timing precision is maintained, but combinational path length is limited
Solution Approach 1:
The patent transforms static timing constraints into dynamic, clock-dependent timing windows. By making the level-shifting circuitry clocked rather than combinational, the system allows variable path lengths as long as data is stable during clocked transparency windows, converting fixed edge-to-edge timing into flexible cycle-based timing.
Solution Approach 2:
The patent requires data to be stable before clock edges and maintains stability during opaque phases, preparing circuits in advance for the next sampling window. This preliminary stabilization allows longer combinational paths to settle their outputs before the next clock cycle begins sampling, effectively borrowing time from subsequent cycles.
3Adaptability or versatility
If time borrowing is enabled in single voltage domain, then timing flexibility is improved, but cross-voltage domain time borrowing is not supported
Solution Approach 1:
The patent designs level-shifting circuitry that simultaneously performs voltage conversion and clocked buffering functions. The same clocked latches and control logic that enable time borrowing within a voltage domain are extended to control cross-voltage domain transfer, making the circuit universal for both single-domain and multi-domain time borrowing operations.
Solution Approach 2:
The patent separates level-shifting functionality into independent clocked stages, each handling specific voltage domain transitions. This segmentation allows time borrowing to be enabled independently in each voltage domain while maintaining proper synchronization at domain boundaries, reducing overall system complexity compared to a monolithic approach.
Data Source
AI summary
Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.