Clock-Synchronized Voltage Monitor for Binary VDD Droop Sensing
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Solution Overview
Problem
Semiconductor devices face issues with VDD droop due to chip activity, leading to timing violations and performance inhibition, which are often addressed by increasing voltage margins, thereby increasing power consumption.
Innovation Solution
A digital voltage monitor with voltage-to-digital converters, digital-to-binary converters, an adder, overshoot and undershoot detectors, and a multiplexer, synchronized with a clock signal, accurately detects VDD droop and outputs it in binary form for easy integration and comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage margin is defined to minimize VDD droop effect on chip performance, then timing violations are reduced, but power consumption increases
Solution Approach 1:
The voltage monitor performs preliminary detection of VDD droop conditions before timing violations occur. By continuously monitoring voltage levels and predicting droop trends, the system can take preventive actions (such as adjusting operating parameters or triggering voltage compensation) before performance degradation happens, thereby maintaining reliability without needing excessive voltage margins that would increase power consumption
Solution Approach 2:
The voltage monitor implements a feedback mechanism that continuously measures actual VDD levels and provides real-time information about voltage droop conditions. This feedback enables dynamic adjustment of operating parameters or voltage compensation strategies based on actual conditions, allowing the system to maintain timing requirements while minimizing power consumption by avoiding unnecessary high voltage margins during periods when droop is not occurring or is within acceptable ranges
2Use of energy by moving object
If accurate voltage monitoring is implemented to detect VDD droop, then power efficiency is optimized, but device complexity increases
Solution Approach 1:
The voltage monitor is designed to be self-calibrating and self-adjusting, using internal reference circuits and automatic gain control mechanisms that eliminate the need for external calibration equipment or complex adjustment mechanisms. The monitor automatically adapts to process variations and temperature changes, reducing the need for additional compensation circuits and thereby limiting the increase in device complexity while maintaining accurate detection capability for optimizing power efficiency
Data Source
AI summary
The present disclosure provides a voltage monitor and a semiconductor device including the voltage monitor. The voltage monitor includes a first voltage-to-digital converter (VDC), a second VDC, a first digital-to-binary converter (DBC), a second DBC, and an adder. The first VDC is configured to generate a first digital signal in response to a clock signal, and the second VDC is configured to generate a second digital signal in response to the clock signal. The first DBC is connected to the first VDC, and configured to convert the first digital signal to a first binary signal. The second DBC is connected to the second VDC, and configured to convert the second digital signal to a second binary signal. The adder is connected to the first DBC and the second DBC, and configured to combine the first binary signal and the second binary signal into an output signal.