Dual-Mode Clocking Switch Impedance Control
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Solution Overview
Problem
Existing clocking systems face inefficiencies due to high resistance and leakage currents in mode switches, which affect power consumption and frequency range support, particularly in dual-mode operations.
Innovation Solution
The use of high impedance voltage sources for gate terminals in a dual-mode clocking system reduces on-resistance and leakage by maintaining near-constant gate overdrive voltage, allowing for improved efficiency in both resonant and conventional modes, and reducing capacitive loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional voltage sources are used to drive switch gates in dual-mode clocking systems, then the switch can be controlled to operate in both resonant and non-resonant modes, but the switch exhibits high on-resistance and high leakage current which reduces power efficiency
Solution Approach 1:
The patent applies parameter changes by using high-impedance voltage sources to dynamically adjust the gate voltage parameters of the switch transistors. The high-impedance sources maintain near-constant overdrive voltage during the on-state, optimizing the balance between on-resistance and leakage current. This parameter optimization directly reduces power loss while maintaining reliable switch operation in both resonant and non-resonant modes
Solution Approach 2:
The patent introduces high-impedance voltage sources as intermediary elements between the control logic and the switch gates. These intermediary sources act as buffer stages that can maintain stable gate voltages with high output impedance, thereby reducing the loading effect on the clock signal while providing precise control over the switch operation. This intermediary approach enables reduced power loss without compromising switch reliability
2Adaptability or versatility
If the switch is designed to support wide frequency range in dual-mode operations, then both resonant and conventional modes can be accommodated, but resistance and leakage currents increase affecting power consumption
Solution Approach 1:
The patent applies dynamics by using high-impedance voltage sources that can dynamically adapt their output characteristics based on the operating mode. In resonant mode, the sources maintain conditions optimal for low loss operation, while in non-resonant mode they adjust to provide stable gate control. This dynamic adaptation enables the switch to maintain low power consumption across a wide frequency range while supporting both operational modes
Solution Approach 2:
The patent utilizes parameter changes by adjusting the gate voltage parameters through high-impedance sources to optimize switch performance for different frequency ranges. The sources maintain near-constant overdrive voltage that adapts to the specific operating conditions, enabling the switch to efficiently operate across both resonant and conventional modes without excessive power consumption
3Device complexity
If standard voltage sources are used for gate control, then circuit complexity is reduced, but capacitive loading increases and efficiency decreases
Solution Approach 1:
The patent introduces high-impedance voltage sources as intermediary buffer stages between the control logic and switch gates. These intermediaries provide high output impedance that minimizes capacitive loading on the clock signal while maintaining stable gate control. Although this adds some circuit complexity, the energy efficiency gains from reduced capacitive loading and optimized switch operation far outweigh the additional complexity
Data Source
Figure 1~2
Figure 3~4
Figure 5~6B
AI summary
A clock system of an integrated circuit includes first (502) and second (504) transistors forming a switch that is used when switching the clock system (Clk) between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal (Clk) and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First (501) and second (503) high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.