Clockless PWM Receiver Using Differential Cyclic Integration
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Solution Overview
Problem
Conventional PWM receivers face challenges in low-power operation without consuming excessive power, particularly in environments where no reference clock is available, and they struggle with varying input frequencies across different modes of operation, leading to high current consumption and area inefficiency.
Innovation Solution
A low-power PWM receiver is designed using a differential cyclic integrator (DCI) that generates distinct voltages for the high and low time periods of PWM signals, allowing efficient demodulation by cycling through states to decode bits without the need for a separate clock, and incorporates a dual latch system for accurate data extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional PWM receiver uses a phase lock loop to demodulate PWM signals without a reference clock, then the receiver can operate without external clock, but the current consumption increases significantly
Solution Approach 1:
The receiver is divided into two functional blocks: a PWM signal generator that creates test PWM signals, and a demodulator that processes received PWM signals. This segmentation allows the system to avoid complex PLL circuits while maintaining the ability to operate without reference clock, thereby reducing current consumption.
Solution Approach 2:
The PWM signal generator uses the received PWM signal itself to generate test signals for demodulation, eliminating the need for separate reference clocks or complex synchronization circuits. This self-service approach reduces component count and power consumption while maintaining adaptability to operate without external clock references.
2Adaptability or versatility
If the PWM receiver operates at higher frequencies to handle varying input frequencies across different modes, then the receiver can support multiple operating modes, but the power consumption increases
Solution Approach 1:
The receiver dynamically adjusts its operation based on the received PWM signal characteristics. The PWM signal generator and demodulator work together to adapt to different input frequencies and duty cycles across various operating modes, allowing the system to maintain optimal performance without continuously operating at maximum frequency, thereby reducing average power consumption.
Solution Approach 2:
The system changes its operational parameters based on the received PWM signal. By monitoring the PWM signal characteristics and adjusting the demodulation process accordingly, the receiver can efficiently handle varying input frequencies across different modes without the need for high-frequency operation in all cases, thus reducing overall power consumption.
3Measurement precision
If a PWM receiver uses over-sampling with high frequency clock to accurately demodulate PWM signals, then the demodulation accuracy improves, but the current consumption increases
Solution Approach 1:
The PWM signal generator acts as an intermediary between the received PWM signal and the demodulator. It generates test PWM signals that facilitate accurate demodulation without requiring high-frequency over-sampling. This intermediary approach maintains demodulation accuracy by creating appropriate test signals while avoiding the need for power-consuming high-frequency clock circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption by approximately half compared to conventional systems while maintaining efficient operation across varying frequencies, effectively addressing the limitations of existing PWM receivers in low-power and high-frequency applications.
Implementation Method 1
The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.
Data Source
AI summary
A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.