Duration/Width Modulated Pulse Demodulation TRIZ Cases

Converts PWM dimming signals to output voltage in one cycle using fixed-ratio counting, avoiding large capacitors and complex LED driver circuits.

Extracts PWM duty cycle digitally to generate stable analog dimming voltage in one cycle without large capacitors or complex peripheral circuits.

Combining pulse width and amplitude modulation lets one carrier transmit independent datasets with higher spectral efficiency and less hardware.

External switch-based frequency adjustment retunes ultrasonic transducers without disassembly, reducing heat, excess current, and service time.

Auto-calibration uses sensor offset nulling and PWM demodulator adjustment to correct temperature and humidity effects in gas sensing.

Temperature and humidity feedback drives PWM offset nulling in a gas sensor, improving leak detection accuracy without complex calibration circuitry.

Dynamic end-of-message timing uses PWM auxiliary symbols to fill allotted transmission time, improving synchronization and bandwidth use.

A long-pulse symbol embeds an extra bit into payload transmission, preserving data rate while enabling reliable CRC, ECC, or control signaling.

An RC ripple and comparator stage lets a PWM filter switch output behavior at a duty-ratio threshold, avoiding fixed 0 V output.

Grouped pulse-width analysis determines symbol rate without a clock estimate, improving accuracy by filtering perturbations and using all pulses.

Optical PWM generation replaces slow comparators to produce narrow, low-distortion RF transmission signals from amplitude and phase data.

A one-sided pulse filter suppresses short PWM pulses and enables accurate, efficient high-gear data recovery without oversampling.

Communication data is embedded in jamming pulses through bandwidth, center-frequency, and pulse-width jitter, preserving jamming while allies detect the signal.

Charge integration on capacitors demodulates PWM without PLL synchronization, cutting power use while tolerating jitter and frequency variation.

A differential cyclic integrator demodulates PWM data without a reference clock, cutting receiver power while handling varying input frequencies.

Measured PWM duty duration lets each node adjust its decoding threshold, improving reliability despite trailing-edge timing variation.

Widening isolated pulses before transmission helps non-linear optical channels resist pulse shrinkage, cut bit errors, and extend link reach.

Adaptive PWM edge timing cuts digital control-loop latency, improving phase margin and transient response without major circuit overhead.

By splitting audio into high and low bands with separate PWM switching frequencies, tuner interference is suppressed without sacrificing playback or efficiency.

Synchronized PWM pulse-pause signaling lets vehicle ECUs share one line, detect errors, and reduce interference in serial data transmission.

Asymmetric edge shaping uses steep leading edges and gradual trailing edges to raise serial data rate without added path noise or overlap.

Multiple delayed drive signals form an embedded FIR filter that suppresses carrier harmonics, shrinking the output filter and preserving bandwidth.

A shared counter drives multiple waveform generators to create synchronized center-aligned PWM with different time profiles for motor control.

Pseudo-random flipping spreads PWM spectral energy, cutting EMI peaks and reducing filter complexity in digital modulation circuits.

A tunable pulse circuit speeds USB signal falling edges by discharging bus capacitance, cutting propagation delay without larger drivers.

An RC capacitor path with phase detection filters high-frequency noise while preserving low-frequency data and reducing circuit area.

Level-coincidence detection and delayed sampling remove spike noise up to ΔT while preserving valid pulses longer than ΔT.

Serial delay stages and switches remove broad glitches while keeping propagation delay controllable across process variations.

Pre-ADC detector estimates predict RF fading and multi-path changes, letting receiver stages adapt early to cut bit errors and processing load.

Weighted delayed square-wave pulses generate accurate UWB impulses while cutting power use and eliminating LO leakage.

Immediate asynchronous PWM duty updates cut control loop lag and prevent missed cycles caused by counter roll over in SMPS control.

A frequency-to-current converter charges a capacitor to create a PWM ramp signal that stays accurate despite component and environmental variation.

Majority logic with SR flip-flops and a delay path suppresses input-signal distortion without the long delay of conventional de-glitching.

Alternating reference voltage comparisons reduces power consumption by 50% while maintaining signal loss detection accuracy.

A glitch suppressing apparatus filters positive and negative glitches using a unified logic circuit with delay elements.