Glitch Suppressing Apparatus Using Unified Logic Circuit
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Solution Overview
Problem
Conventional glitch suppressing circuits require two separate circuits for filtering positive and negative glitches, leading to increased chip area usage and inefficiencies in filtering both types of glitches when they coexist.
Innovation Solution
A single glitch suppressing apparatus utilizing a specific configuration of switches, delay circuits, logic circuits, and inverters, including N-type and P-type transistors, to filter both positive and negative glitches within the same circuit, reducing chip area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate circuits are used to filter positive and negative glitches, then filtering effectiveness is improved, but chip area increases
Solution Approach 1:
The patent combines the functions of positive glitch filtering and negative glitch filtering into a single integrated circuit. The circuit uses a unified structure with delay elements and logic gates that can simultaneously handle both positive and negative glitch suppression, thereby reducing chip area while maintaining filtering effectiveness.
Solution Approach 2:
The single circuit is designed to perform multiple functions: it can filter positive glitches, filter negative glitches, and adapt to different glitch widths through configurable delay elements. This multi-functional design eliminates the need for separate dedicated circuits for each glitch type.
2Reliability
If delay time is increased to filter glitches effectively, then filtering performance is improved, but circuit response time increases
Solution Approach 1:
The circuit employs configurable delay elements that allow the delay time to be adjusted according to the specific application requirements and glitch characteristics. This dynamic adjustment capability enables optimization between filtering performance and response time, rather than being fixed at a single delay value.
Solution Approach 2:
The patent changes the delay time parameter to match different glitch widths. By adjusting this critical parameter, the circuit can effectively filter various types of glitches while minimizing the impact on normal signal response, thus balancing filtering performance with response time.
Data Source
AI summary
A glitch suppressing apparatus is provided. The glitch suppressing apparatus comprises four N-type transistors, four P-type transistors, a first delay circuit, a second delay circuit, a first logic circuit, a second logic circuit and two inverters. The glitch suppressing apparatus uses the specific connection relations and functions of the above components to filter positive glitches and negative glitches in the same circuit, so that the glitch suppressing apparatus can be implemented on a smaller chip area.