Syncless PWM Receiver Circuit for Jitter-Tolerant Demodulation
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Solution Overview
Problem
Existing methods for capturing pulse width modulated (PWM) data signals in mobile processing environments require synchronization and generate high power consumption, especially when using phase-locked loops (PLL) or counters, and are not tolerant to frequency jitter and variation.
Innovation Solution
A PWM receiver circuit that operates without synchronization, consumes less power, and is tolerant to frequency jitter and variation, using constant current sources and capacitors to integrate charges during high and low periods of the PWM signal, eliminating the need for a local clock signal and reducing the complexity of circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to capture PWM data signals, then the signal can be synchronized and demodulated, but the power consumption increases significantly
Solution Approach 1:
The patent extracts and eliminates the PLL synchronization mechanism from the PWM receiver, replacing it with a synchronization-free sampling approach that uses a simple counter and comparator, thereby removing the high power consumption component while maintaining signal capture capability
Solution Approach 2:
The receiver circuit uses the PWM signal itself to control the sampling process through its inherent edges, eliminating the need for external synchronization signals or complex locking mechanisms, allowing the system to serve itself without additional power-hungry synchronization circuitry
2Measurement precision
If a counter with high frequency clock signal is used to demodulate PWM signals, then the demodulation accuracy improves, but the power consumption increases
Solution Approach 1:
The patent employs periodic sampling action triggered by PWM signal edges rather than continuous high-frequency clocking, achieving accurate demodulation through strategically timed samples that capture the essential duty cycle information without requiring sustained high-frequency operation
Solution Approach 2:
The system uses a counter that counts for a limited number of clock cycles (partial action) rather than requiring the full high-frequency clock operation continuously, achieving sufficient counting precision for demodulation while consuming less power by limiting the counting duration
3Reliability
If a PLL or counter-based synchronization method is used, then the PWM signal can be captured accurately, but the circuit complexity increases
Solution Approach 1:
The patent removes the PLL synchronization block and complex clock generation circuitry from the receiver design, retaining only the essential sampling and demodulation functions that can be implemented with simpler counters and comparators, thereby reducing overall circuit complexity
Solution Approach 2:
The simplified receiver circuit uses multi-functional blocks where the counter serves both as a sampling timer and a duty cycle measurement device, and the comparator performs both threshold detection and data output generation, reducing the total number of dedicated circuit components
4Reliability
If a synchronization preamble is added to the PWM signal, then the receiver can synchronize with the signal, but the bandwidth efficiency decreases
Solution Approach 1:
The receiver automatically adapts to the incoming PWM signal characteristics through edge-triggered sampling that uses the signal's own transitions as synchronization points, eliminating the need for external synchronization preambles and allowing immediate data transmission without bandwidth-wasting training sequences
Solution Approach 2:
The circuit performs preliminary setup by configuring its sampling edges and counter initialization based on the first detected PWM transitions, enabling immediate accurate demodulation without requiring pre-transmitted synchronization patterns that would consume bandwidth
5Adaptability or versatility
If the receiver is designed to be tolerant of frequency variation, then it can handle jitter and variation, but the demodulation precision may be compromised
Solution Approach 1:
The receiver dynamically adjusts its sampling timing based on the actual PWM signal frequency and duty cycle variations, using edge-triggered sampling that automatically adapts to frequency changes rather than relying on fixed timing, thereby maintaining precision across a range of frequencies
Solution Approach 2:
The system changes its operational parameters (sampling edge timing, counter reset points) based on the detected PWM signal characteristics, allowing it to maintain accurate demodulation precision even when the input frequency varies or contains jitter
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable demodulation of PWM signals without synchronization, reduces power consumption, and can handle a wide range of frequency variations, making it suitable for burst-then-stall intermittent communications and various duty cycles.
Implementation Method 1
A first constant current source is coupled in series with a first switch and a first capacitor between a supply voltage and ground. A second constant current source is coupled in series with a second switch and a second capacitor between the supply voltage and ground.
Data Source
AI summary
A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.