Spike Noise Elimination Circuit for Accurate Short-Pulse Signal Filtering
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Solution Overview
Problem
Conventional spike noise eliminating circuits malfunction when faced with signals having pulse widths between ΔT and 2ΔT, failing to accurately eliminate noise and transmit regular signals within this range.
Innovation Solution
A spike noise eliminating circuit that detects coincidence in level between the input signal and a first delay signal, and samples the input signal based on a second delay signal, ensuring precise elimination of noise with pulse widths up to ΔT and proper transmission of signals with wider pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CR delay circuit is used to eliminate spike noise, then spike noise can be eliminated, but integration is difficult and delay amount accuracy is insufficient
Solution Approach 1:
The patent replaces the analog CR delay circuit with a digital delay gate circuit. Instead of using physical resistors and capacitors, the invention uses digital logic gates (AND gates, OR gates, NOT gates) and delay elements to achieve the same spike noise elimination function. This substitution enables easy integration into digital systems while maintaining the noise elimination capability.
Solution Approach 2:
The patent changes the delay amount parameter by using multiple delay gates with different delay times (T1, T2, T3 where T1 < T2 < T3). This allows precise control of the delay amount to match the spike noise duration, improving both the accuracy of noise elimination and the adaptability to different noise conditions.
2Reliability
If a conventional CR delay circuit is used to eliminate spike noise, then spike noise can be eliminated, but delay amount accuracy is insufficient
Solution Approach 1:
The patent uses multiple delay gates with precisely controlled different delay times (T1, T2, T3) to achieve accurate delay amount control. By adjusting these delay parameters, the circuit can precisely match the spike noise duration, ensuring accurate noise elimination without affecting valid signals.
Solution Approach 2:
The patent divides the delay function into multiple separate delay gates instead of using a single CR circuit. Each delay gate provides a specific delay time, and their outputs are combined through logic gates. This segmentation allows independent optimization of each delay stage, improving overall delay accuracy.
3Reliability
If a digital spike noise eliminating circuit with multiple delay gates is used, then spike noise elimination is improved, but signals with pulse widths between ΔT and 2ΔT cannot be accurately transmitted
Solution Approach 1:
The patent makes the delay amount dynamic and adjustable by providing multiple delay gates with different delay times (T1, T2, T3) that can be selected based on the actual spike noise duration. This dynamic adjustment capability allows the circuit to adapt to different noise conditions while preserving valid signals with various pulse widths, resolving the contradiction between noise elimination accuracy and signal transmission fidelity.
Solution Approach 2:
The patent performs preliminary delay of the input signal by multiple predetermined amounts before comparison. By pre-calculating and providing multiple delay versions of the signal, the circuit can quickly determine which delay amount best matches the noise duration without requiring real-time adjustment, thus maintaining both noise elimination accuracy and signal transmission integrity.
4Reliability
If the input signal is delayed by a fixed amount, then spike noise can be eliminated, but the delay amount cannot be adjusted for different noise durations
Solution Approach 1:
The patent transforms the fixed delay system into a dynamic, adjustable one by providing multiple delay gates with different delay times (T1, T2, T3). The circuit can select the appropriate delay amount based on the actual spike noise duration, enabling adaptation to various noise conditions while maintaining effective noise elimination.
Solution Approach 2:
The patent creates a universal spike noise elimination circuit that can handle different noise durations by incorporating multiple delay gates. This multi-functional design allows the same circuit structure to eliminate various types of spike noise (with different durations) by selecting the appropriate delay path, improving versatility without sacrificing noise elimination effectiveness.
Data Source
AI summary
There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.