USB Fall Time Accelerator Circuit for Bus Capacitance Discharge
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Solution Overview
Problem
Existing solutions for mitigating excessive capacitive loading in USB interfaces, such as rise time accelerators and re-clocking, either only address the rising edge of signals or require impractical design changes like shorter cable runs or larger transistors, leading to increased power consumption and propagation delays.
Innovation Solution
A fall time accelerator circuit is introduced, comprising a pulse signal generator, active timer, and falling drive signal strengthener, which detects the falling edge of a digital signal, generates a tunable pulse, and releases it onto the USB bus to efficiently discharge bus capacitance, using resistive coupling and pulse width tuning for bidirectional applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If line driving transistors are made large to reduce signal propagation delay time, then propagation delay is reduced, but chip area increases and power consumption increases
Solution Approach 1:
The fall time accelerator circuit segments the capacitance discharge function into distinct components: a pulse signal generator creates timed pulses, an active timer controls pulse duration, and a falling drive signal strengthener amplifies the discharge effect. This segmentation allows effective capacitance discharge without requiring large transistors, thus reducing chip area while maintaining fast fall times.
Solution Approach 2:
The circuit uses periodic pulse signals generated by the pulse signal generator to actively discharge bus capacitance during falling edges. This periodic action replaces the need for continuously large transistors, achieving fast signal transitions with smaller, more power-efficient components.
2Reliability
If buffers are placed in series along the wiring route to improve signal timings, then signal timing is improved, but propagation delay increases due to additional contacts and circuit complexity
Solution Approach 1:
The fall time accelerator circuit acts as an intermediary component that selectively enhances falling edges without disrupting the overall signal path. By inserting this dedicated capacitance discharge circuit rather than multiple buffers, the solution improves signal timing while minimizing additional propagation delay and contact resistance.
3Quantity of substance
If rise time accelerators are used to decrease excessive bus capacitance, then bus capacitance is reduced, but only the rising edge of signals is affected not the falling edge
Solution Approach 1:
Instead of adapting rise time accelerator technology to handle falling edges, the invention inverts the approach by designing a dedicated fall time accelerator that specifically targets falling edge enhancement. The circuit uses a pulse signal generator and active timer to create downward pulses that actively discharge capacitance during falling edges, providing symmetric treatment to both rising and falling edges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fall time accelerator circuit effectively minimizes propagation delays by accelerating the fall time of signals, reducing the adverse effects of excessive bus capacitance without increasing power consumption or complexity, thus improving signal quality in USB interfaces.
Implementation Method 1
The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path
Implementation Method 2
The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time
Implementation Method 3
Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus
Data Source
AI summary
Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.