De-Glitch Circuit Using Majority Logic Without Signal Delay
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Solution Overview
Problem
Conventional de-glitch circuits delay digital logic signals by a predetermined time period, which can hinder the operation of certain digital logic circuits, as they remove glitches by requiring a change in the input signal to persist for a specific duration before propagating to the output.
Innovation Solution
A digital logic circuit and method that removes distortion without delaying the signal by using first and second Set-Reset flip-flops, a delay circuit, and a majority circuit to recognize initial transitions and ignore subsequent transitions until a delay period has passed, ensuring that reflections or distortion subside, thereby preventing logic errors without substantial delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional de-glitch circuits require a change in input signal to persist for a predetermined time period before propagation, then glitches are removed from the signal, but the signal is delayed by a time greater than or equal to the de-glitching period
Solution Approach 1:
The circuit performs preliminary detection of signal transitions using edge-triggered D flip-flops that capture the state of the input signal at specific clock edges. This preliminary action allows the circuit to identify valid transitions before they would cause glitches, enabling glitch removal without delaying the output signal beyond the clock period.
Solution Approach 2:
The circuit uses feedback through the clock signal and flip-flop outputs to monitor and control signal transitions. The clocked architecture provides feedback mechanisms that ensure only valid, sustained transitions are propagated, while transient glitches are suppressed, achieving both reliability improvement and minimal delay.
2Reliability
If the de-glitching period is extended to remove more distortion, then signal reliability improves, but the delay increases making the circuit unsuitable for certain digital logic applications
Solution Approach 1:
The circuit performs preliminary detection of signal transitions using edge-triggered D flip-flops that capture the state of the input signal at specific clock edges. This preliminary action allows the circuit to identify valid transitions before they would cause glitches, enabling glitch removal without delaying the output signal beyond the clock period.
Solution Approach 2:
The circuit changes the parameter of distortion filtering from time-duration-based (conventional de-glitching) to state-based (flip-flop sampling). By sampling the signal state at clock edges rather than holding it for a predetermined period, the circuit achieves effective glitch removal while maintaining signal propagation speed within the clock period.
Data Source
AI summary
A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.