Sliding Error Sampler Timing for Low-Latency PWM Control Loops
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Solution Overview
Problem
Digital control loops in applications like switching power supplies and robotic controllers face latency issues due to long pipeline delays, which impair phase and gain margins, leading to suboptimal performance compared to analog loops.
Innovation Solution
The implementation of a sliding error sampler with adaptive timing in digital control loops, where the clock cycles for the digital pulse width modulator are varied based on previous outputs, and a margin is added to accommodate transient conditions, effectively reducing latency by sliding the sampling and conversion processes towards the output edge of the pulse width modulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If digital control loops use fixed pipeline delays for processing, then circuit simplicity is maintained, but loop latency increases reducing phase and gain margins
Solution Approach 1:
The patent implements dynamic timing adjustment where the digital pulse width modulator adapts its output timing based on previous iteration results. The trailing edge of the PWM output is adjusted variable depending on the previous iteration pulse width, creating a dynamic system that optimizes latency while maintaining stability through adaptive rather than fixed timing
Solution Approach 2:
The patent uses prediction of computation time for the proportional-integral-derivative filter based on average values from previous digital pulse width modulator outputs. This preliminary estimation allows the system to prepare timing adjustments in advance, reducing actual loop latency by anticipating processing requirements before they occur
2Loss of time
If digital control loops reduce pipeline delays to minimize latency, then loop latency decreases improving phase and gain margins, but power consumption and circuit complexity increase
Solution Approach 1:
The patent changes the timing parameters of the digital pulse width modulator dynamically based on previous iteration performance. By adjusting the trailing edge timing and using predicted computation times, the system optimizes latency without requiring additional parallel circuitry that would increase power consumption. The margin added to accommodate transient conditions is adjusted based on previous iteration pulse width, optimizing the balance between latency reduction and power efficiency
Data Source
AI summary
A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation time for the proportional-integral-derivative filter is predicted based on an average for previous digital pulse width modulator outputs, computed within the integral path for the previous loop iteration. A margin is added to accommodate transient conditions accelerating the trailing edge of the digital pulse width modulator output, either fixed or variable depending on the previous iteration pulse width.