CML-to-CMOS Converter Feedback for 50% PLL Clock Duty Cycle
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Solution Overview
Problem
High-frequency PLLs in ASICs face challenges in maintaining a tight duty cycle specification of 45-55% for the output clock signal due to transistor mismatches and input signal mismatches, leading to an increased spread in the duty cycle of the output clock.
Innovation Solution
A CML-to-CMOS converter circuit is designed with a limiting differential amplifier, low-pass filter, and a second differential amplifier to generate a single-ended clock signal with a desired duty cycle, using a differential bias current signal to correct the duty cycle by altering the operating points of transistors, and a reference voltage to set the desired duty cycle, typically 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If small geometries are used in the PLL circuit to achieve frequencies of up to 1 GHz, then the operating frequency is improved, but the mismatch between transistors and the mismatch in input signals causes increased spread in the duty cycle of the output clock
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle of the output clock signal is measured and fed back to a control circuit. This control circuit adjusts the bias currents of the CML-to-CMOS converter to correct duty cycle deviations, thereby maintaining precise duty cycle control even at high operating frequencies where transistor mismatch occurs
Solution Approach 2:
The patent dynamically changes the bias current parameters of the CML-to-CMOS converter based on the measured duty cycle. By adjusting these electrical parameters in real-time, the system compensates for transistor mismatch effects and maintains the desired duty cycle specification while operating at high frequencies
2Adaptability or versatility
If a CML-to-CMOS converter is used to convert CML differential voltage levels to CMOS compatible voltage levels, then the voltage level compatibility is improved, but the duty cycle of the output clock signal deviates from the desired 50% specification
Solution Approach 1:
The patent employs a feedback loop that continuously monitors the duty cycle of the output clock signal from the CML-to-CMOS converter and adjusts the converter's operating parameters accordingly. This feedback mechanism enables the system to maintain both voltage level compatibility and precise 50% duty cycle accuracy simultaneously
Solution Approach 2:
The patent replaces fixed, hardwired duty cycle adjustment mechanisms with a dynamic electrical control system. By using voltage-controlled current sources and feedback-based parameter adjustment, the system achieves precise duty cycle control without requiring mechanical or fixed circuit modifications, thereby maintaining voltage compatibility while correcting duty cycle deviations
Data Source
AI summary
Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier. According to another embodiment, a CML-to-CMOS converter circuit is described, including a limiting differential amplifier for generating a single ended clock signal from a differential common mode clock signal, wherein the single ended clock signal has a duty cycle, a low-pass filter for generating a measurement of the duty cycle of the single ended clock signal, and a second differential amplifier for (i) comparing the measurement with a reference voltage and (ii) generating a differential bias current signal in response to the comparison.