CML-to-CMOS Deserializer with Shared Final Conversion Stage
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Solution Overview
Problem
Conventional deserializers face challenges in efficiently converting high-speed serial links from current-mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) while minimizing power consumption and area, as they require separate CML-to-CMOS converters for each parallel data stream, leading to increased power and area usage.
Innovation Solution
The proposed CML-to-CMOS deserializer employs a multi-stage architecture with level shifting circuitry and source follower-based level shifters to reduce common mode voltage, allowing for a single final stage to perform both deserialization and CML-to-CMOS conversion, thereby reducing power consumption and area by eliminating the need for separate CML-to-CMOS converters for each data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate CML-to-CMOS converters are used for each parallel data stream, then conversion accuracy is improved, but power consumption and area increase
Solution Approach 1:
The patent merges the CML-to-CMOS conversion function with the deserialization function by integrating a single CML-to-CMOS converter at the output of the deserializer. This single converter serves all parallel data streams simultaneously, eliminating the need for separate converters for each stream. The conversion accuracy is maintained because the integrated converter is designed to handle the converted signals properly, while power consumption and area are reduced by sharing the conversion resources across all data streams.
Solution Approach 2:
The deserializer output stage is designed to perform multiple functions: it both deserializes the incoming serial data into parallel streams and performs the CML-to-CMOS conversion for all streams simultaneously. This multi-functional design eliminates redundant circuitry and reduces overall power consumption while maintaining conversion accuracy through proper signal level translation.
2Reliability
If separate CML-to-CMOS converters are used for each parallel data stream, then conversion reliability is improved, but device area increases
Solution Approach 1:
The patent combines multiple conversion functions into a single CML-to-CMOS converter located at the deserializer output. This single converter handles all parallel data streams simultaneously, reducing the total device area required compared to having separate converters for each stream. Conversion reliability is maintained through proper design of the integrated converter to ensure accurate signal translation for all streams.
3Speed
If CML operation is used for high-speed data transmission, then data rate is improved, but compatibility with CMOS processing decreases
Solution Approach 1:
The patent introduces a CML-to-CMOS converter as an intermediary device between the high-speed CML serial link and the CMOS processing domain. This converter acts as a bridge that translates CML signals to CMOS-compatible voltage levels, enabling high-speed data transmission while maintaining compatibility with standard CMOS digital signal processing circuits. The converter ensures proper signal level translation and impedance matching between the two domains.
Data Source
AI summary
An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.