CML Multi-Tap Feed-Forward Equalizer for Pre-Cursor ISI
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Solution Overview
Problem
High-speed data transmission systems face challenges with inter-symbol interference (ISI) due to dispersive channels, where existing feed-forward equalizers (FFE) consume power, struggle to control delay elements, and cannot effectively compensate for pre-cursor ISI, and XOR gates degrade signals and add jitter.
Innovation Solution
A method using a current mode logic (CML) summing amplifier with multiple taps as a feed-forward equalizer, generating a temporal sequence of past, present, and future signals, and selectively weighting these signals to produce a summed output, enabling optimal equalization performance across dispersive channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional FFE with multiple delay stages is used to compensate for ISI, then the equalization capability is improved, but the power consumption increases and delay control becomes difficult
Solution Approach 1:
The patent changes the fundamental operating parameters of the FFE by using current mode logic summing amplifiers with programmable tap weights instead of traditional voltage mode delay stages. This allows direct control of equalization coefficients through current weighting, eliminating the need for multiple controlled delay elements and reducing power consumption while maintaining equalization capability.
Solution Approach 2:
The patent replaces the mechanical/electrical delay stage structure with a signal processing approach using summing amplifiers. Instead of physically delaying signals through multiple stages, the system uses current-weighted summation of tapped signals to achieve the same equalization effect with lower power consumption and simpler control.
2Reliability
If traditional FFE circuitry is used, then post-cursor ISI can be compensated, but pre-cursor ISI compensation is not possible
Solution Approach 1:
The patent creates a universal FFE structure using current mode summing amplifiers that can handle both pre-cursor and post-cursor ISI compensation. The programmable tap weights allow the same circuit architecture to adapt to different equalization needs, providing multi-functionality that traditional FFE designs lack.
Solution Approach 2:
The patent introduces dynamic control of tap weights through programmable current sources in the summing amplifiers. This allows the equalizer to adaptively adjust its response to compensate for both pre-cursor and post-cursor ISI by dynamically changing the weighting coefficients based on channel conditions.
3Extent of automation
If XOR gates are used in the high speed signal path for signal processing, then logic operations are performed, but signal degradation and jitter are introduced
Solution Approach 1:
The patent replaces XOR gate logic operations with current mode summing amplifier circuitry. Instead of using digital logic gates that degrade high-speed signals, the system uses analog current summation to achieve the same signal processing function with superior signal integrity and reduced jitter.
Solution Approach 2:
The patent introduces current mode summing amplifiers as intermediary elements between the tapped delay lines and the output. These amplifiers serve as a mediator that performs the necessary signal processing operations without directly processing the high-speed digital signals, thereby preventing signal degradation and jitter introduction.
Data Source
AI summary
A system and method are provided for feed-forward equalization (FFE) in a transmission system. The method accepts a serial stream of input digital data signals. For each input data signal, a temporal sequence of signals is generated. Each of the signals in the temporal sequence is selectively shaped. Shaping map include varying the degree of amplification, modifying the slew rate, or varying the time delay. The contributions of the selectively shaped signals in the temporal sequence are then selectively weighted, and a summed output signal is transmitted.