CML Gate Layout With Separated Paths for Single-Event Resistance
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Solution Overview
Problem
Current-mode-logic (CML) gates in electronic circuits are vulnerable to single-event effects such as single-event upsets (SEU) and single-event transients (SET), leading to unwanted changes in memory elements, which increases power consumption and is not suitable for small technology nodes, and existing solutions require additional power and larger components to prevent errors.
Innovation Solution
Manufacturing CML gates with physically separated and identical electronic paths to prevent the propagation of errors, allowing for reduced current usage and lower energy consumption, while also enabling detection of single-event effects by comparing output signals from multiple paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the current passing through CML gates is increased to prevent SEU and SET errors, then the reliability of the circuit is improved, but the power consumption increases and the circuit becomes unsuitable for small technology nodes
Solution Approach 1:
The circuit is divided into multiple identical electronic paths that are physically separated. Each path processes the same input signal independently, and their outputs are compared to detect single-event effects. This segmentation allows the circuit to achieve higher reliability through error detection without requiring increased current in each individual path, thus avoiding the power consumption penalty.
2Reliability
If additional CML gates are added to prevent error propagation, then the reliability is improved, but the power consumption increases, the manufacturing cost increases, and the circuit footprint increases
Solution Approach 1:
The circuit uses multiple identical electronic paths that can be implemented using the same standard cells or logic units. This segmentation approach achieves error detection capability without requiring additional complex error correction logic, thereby improving reliability while minimizing increases in device complexity and component count.
Solution Approach 2:
Instead of adding complex error correction circuits, the invention creates identical copies of the electronic path and compares their outputs. This copying strategy provides robust error detection with minimal additional complexity, as the copied paths use the same proven design rather than introducing new complex error handling logic.
Data Source
AI summary
A current-mode-logic gate designed to have a first electronic path and a second electronic path. Each electronic path has a pair of transistors. The second electronic path is physically separated and identical to the first electronic path. In operation, a first input signal is transmitted through the first electronic path of the current-mode-logic gate to produce a first output signal. Similarly, a second input signal is transmitted through the second electronic path of the current-mode-logic gate to produce a second output signal.