CMOS Structure With Asymmetric Gate Electrodes for High Voltage
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Solution Overview
Problem
Existing CMOS devices, particularly high-voltage CMOS devices, face challenges in efficiently managing high voltages due to limitations in gate dielectric thickness and material usage, which affects their reliability and manufacturing complexity.
Innovation Solution
A semiconductor structure comprising a CMOS structure with a PMOS and NMOS configuration, where the PMOS has a fully silicided gate electrode and the NMOS has a non-silicided conductive gate electrode, both with partially embedded gate dielectrics in the substrate, optimized for high voltage resistance and simplified manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional gate dielectric structures are used in high voltage CMOS devices, then manufacturing complexity increases due to additional doped channel regions and ion implantation steps, but high voltage resistance is compromised
Solution Approach 1:
The gate dielectric is segmented into two distinct regions: a first gate dielectric region with greater thickness for high voltage resistance, and a second gate dielectric region with lesser thickness. This segmentation allows each region to be optimized for its specific function, enabling high voltage operation without requiring complex additional processing steps
Solution Approach 2:
Different regions of the gate dielectric are assigned different thicknesses and properties: the first gate dielectric region has greater thickness specifically positioned to handle high voltage stress, while the second region has lesser thickness. This local differentiation of quality allows the structure to achieve high voltage resistance without uniformly increasing complexity across the entire device
2Reliability
If gate dielectric thickness is increased to improve high voltage resistance, then manufacturing complexity increases due to additional processing steps
Solution Approach 1:
The formation of the dual-region gate dielectric structure is merged with the standard CMOS fabrication process flow. The first and second gate dielectric regions are formed using integrated processing steps that combine multiple functions into unified operations, avoiding the need for separate additional processing stages and maintaining manufacturing simplicity
3Reliability
If fully silicided gate electrode is used for PMOS, then high voltage resistance is improved, but manufacturing complexity increases
Solution Approach 1:
The gate electrode structure exhibits asymmetry between PMOS and NMOS regions: the PMOS gate electrode is fully silicided to enhance high voltage resistance, while the NMOS gate electrode maintains a different configuration. This asymmetric treatment allows optimization for high voltage operation in the PMOS region without imposing the same complexity on the NMOS region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances resistance to high voltages, simplifies the manufacturing process, reduces costs, and improves reliability by avoiding the need for additional doped channel regions and ion implantation through the gate dielectric.
Implementation Method 1
a fully silicided gate electrode disposed on the first gate dielectric
Data Source
AI summary
A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.