CMOS Image Sensor Asymmetric Well Structure Source Follower

The patent applies asymmetry by configuring the well structure differently for the drive transistor and select transistor. Specifically, the well under the drive transistor has a first width while the well under the select transistor has a second width that is narrower than the first width. This asymmetric configuration reduces the potential barrier in the source follower, thereby minimizing dead zone signal variation and improving image sensitivity while maintaining manufacturing feasibility through a systematic well formation process.

The patent applies local quality by making the well structure width position-dependent. The well width is specifically narrowed only in the region under the select transistor while maintaining a standard width under the drive transistor. This localized modification targets the specific area where potential barrier reduction is needed to minimize dead zone signal variation, without requiring complex asymmetric structures throughout the entire device, thus balancing performance improvement with manufacturing complexity.

The patent applies parameter changes by modifying the well structure width parameter to optimize the source follower characteristics. By narrowing the well width under the select transistor, the potential barrier is reduced, which improves signal transfer efficiency and enhances photosensitivity. This parameter modification allows the photodiode to achieve better light detection capability without requiring an increase in photodiode area, thus maintaining the fill factor within acceptable constraints while improving overall image sensor performance.