Transistor TRIZ Cases

An oxide separation region decouples the fin channel from the substrate, improving gate control and current efficiency during aggressive gate length scaling.

Varying wall oxide film thickness mitigates gate disturbances from neighbor and passing gates by applying local quality to different sidewall locations.

Self-aligned top gate oxide semiconductor transistor minimizes parasitic capacitance and simplifies low-temperature manufacturing.

A semiconductor device uses a gate insulating layer with non-uniform thickness to form lateral double diffused metal oxide semiconductor field effect transistors.

A semiconductor device uses organic material inside a resin film through hole to form source and drain electrodes along the inner wall.

An oxide layer shields metal barriers from etchant damage, preventing intrusion into gate dielectrics and reducing device defects.

Epitaxial gate growth maintains electrical reliability while reducing device dimensions and process complexity.

A ring-shaped gate DMOS device positions the lightly doped drain apart from corners to maintain higher threshold voltage.

A symmetric vertical nanowire SRAM cell layout arranges transistors to enhance device reliability.

TFT memory cells flank a logic layer to increase density while reducing standby power from access leakage.

A rear surface irradiation configuration places wiring on the substrate front to maximize the photoelectric conversion area.

A suspended membrane dual-gate MOS transistor forms a single-crystal semiconductor layer anchored in an insulating ring.

Segmented etching reduces fin asymmetry and degradation during spacer isolation in integrated circuits.

Dual bias voltage plasma doping implants dopant ions into non-planar semiconductor bodies to reduce vertical straggle and improve uniformity.

Composite protective layer prevents semiconductor de-oxygenation, resolving the trade-off between etching speed and TFT stability.

LDNMOS device lowers breakdown voltage via metal overlap with isolation structure, maintaining reliability without shrinking dimensions.

Segmented work function metallic layers enable precise threshold voltage control in SRAM metal gate transistors.

A P+NPN varactor diode structure with hyper-abrupt doping profiles optimizes capacitance variation.

Anti-series diodes and series resistor protect GaN field-effect transistors from electrostatic discharge.

A thin film transistor substrate integrates a light-blocking layer beneath the active semiconductor region to shield it from backlight radiation.

A solid-state image sensing device uses a high-dielectric insulative film to lower contact resistance at the floating diffusion electrode.

Cell current-distributing conductive patterns enhance electroplating current distribution in semiconductor devices.

Interleaved active regions and conductive layers reduce source-to-source on-resistance by 26% without thinning the wafer, avoiding mechanical cracking risks.

A transistor structure uses a carrier transit layer to reduce contact resistance between electrodes and the channel.

Outer sidewalls on second MIS transistors block stress transfer, preventing driving force reduction without extra process steps.

Segmented lead loops allow defective package removal without disrupting adjacent electrical connections.

Hydrogen-rich silicon nitride sidewall spacers reduce interface trap density and channel defectivity in PMOS devices.

Vertical fins and segmented gates in a 3D FinFET structure minimize transistor area, resolving storage density limits in DRAM.

Self-aligned anisotropic etching back creates uniform word lines, reducing contact resistance and misalignment without photolithography.

A silicon-on-insulator memory device uses floating gates to trap charge between semiconductor regions.

Varied MOS transistor gate lengths reduce back bias effects and minimize circuit area while maintaining high current driving performance.

Offset interconnects vary pitch across memory die layers to reduce manufacturing costs while maintaining high bandwidth.

Optimized standard cell layout reduces area and fabrication variations by merging transistor connections to feedback nodes.

An integrated circuit protection device combines a negative temperature coefficient thermistor and a fuse element in series to limit initial inrush currents.

Substituting metal nanowires for semiconductor interconnects reduces chip area while maintaining device reliability.

Narrowing the select transistor well reduces potential barriers, enhancing image sensitivity and dynamic range.

A castellated gate contact surrounds ridge channels in a GaN heterostructure to enable enhancement mode operation.

Silicon nitride hard mask preserves polysilicon control gates during replacement gate processing, preventing leakage from excessive material loss.

A pixel circuit merges writing and threshold compensation transistor source-drain regions into a common diffusion layer to stabilize gate-source voltage.

A transistor using an oxide semiconductor with a c-axis aligned crystal structure to enhance carrier control and reduce parasitic capacitance.

Segmented etching steps with distinct polymer layers reduce spatial variations in fin height while maintaining high productivity.

Dummy gate replacement forms metal gates while fin recessing creates precise source-drain epitaxy geometry for improved carrier mobility.

Merges coupling capacitor with guard ring poly gate to minimize layout region consumption while maintaining robust electrostatic discharge protection.

Segmented charge storage regions concentrate electrons in a middle layer to resolve the contradiction between fast programming and data retention.

A transistor uses oxide semiconductor crystal grains with varying equivalent circle diameters to reduce defects.

An intermediary stress-releasing transistor prevents oxide breakdown on the select transistor during program operations.