GaN HEMT Castellated Gate for E-Mode Integration

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Solution Overview

Problem

Current GaN HEMTs operate in depletion mode, requiring a negative gate bias to turn off, which limits their integration with silicon-based CMOS devices and efficiency in DC-DC power conversion, as they are normally on and require level shifters for compatibility.

Innovation Solution

Simultaneously fabricating integrated GaN circuits with both enhancement mode (e-mode) and depletion mode (d-mode) high electron mobility transistors (HEMTs) using a castellated channel device with a three-sided conductive gate contact that surrounds the ridge channels, allowing for e-mode operation without level shifters and efficient DC-DC power conversion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If depletion mode HEMTs are used, then the device is normally on and easy to manufacture, but it requires negative gate bias to turn off and needs level shifters for CMOS compatibility

Engineering Contradiction:

Improveease of manufactureVSAvoiddevice complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The gate contact is segmented into a three-sided castellated structure that surrounds the channel on top and sides, creating distinct enhancement mode regions. This segmentation allows the device to achieve normally-off operation while maintaining compatibility with standard fabrication processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate contact extends from a traditional planar configuration into the third dimension by surrounding the channel on multiple sides (top and lateral surfaces). This dimensional change enables enhancement mode operation through multi-faceted gate control of the channel

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Device complexity

If depletion mode HEMTs are used, then the device structure is simple, but it requires level shifters for interfacing with silicon-based CMOS devices

Engineering Contradiction:

Improvedevice complexityVSAvoidadaptability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The heterostructure employs local compositional variations in the barrier layer, with different aluminum compositions in different regions to create both enhancement mode (castellated) and depletion mode (planar) devices within the same structure, enabling adaptability to different circuit requirements

Inventive Principle:

Principle #3Local quality

3Loss of energy

If enhancement mode devices are implemented, then level shifters can be eliminated and DC-DC power conversion efficiency improves, but the fabrication process becomes more complex

Engineering Contradiction:

Improveenergy lossVSAvoidease of manufacture

Core Design Contradiction:

Loss of energyVSEase of manufacture

Solution Approach 1:

The patent merges enhancement mode and depletion mode device fabrication into a single integrated process flow. The castellated gate pattern is formed using the same epitaxial growth and lithography steps as planar gates, combining the benefits of both device types without requiring separate fabrication lines

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The heterostructure design provides universal functionality by incorporating both enhancement mode (normally-off) and depletion mode (normally-on) devices in the same structure, allowing the system to optimize for different operating conditions and applications

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the elimination of level shifters, improves the efficiency of DC-DC power conversion, and simplifies mixed-signal and RF circuits by allowing direct integration of GaN-based logic circuits, enhancing the versatility and performance of GaN-based circuits.

Implementation Method 1

Certain heterostructure materials, such as Aluminum Gallium Nitride (AlGaN) and Gallium Nitride (GaN), create an electron well (i.e., a sheet of electrons) at the interface between the two dissimilar materials resulting from the piezoelectric effect and spontaneous polarization effect therebetween.

Methodology Applied

Scientific EffectPiezoelectric effect: Piezoelectric Effect

Implementation Method 2

Methodology Applied

Scientific EffectSpontaneous polarization effect: Polarisation

Data Source

PatentUS10854600B2Integrated enhancement mode and depletion mode device structure and method of making the same

Publication Date: 2020.12.01 NORTHROP GRUMMAN SYSTEMS CORP

AI summary

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.