Stacked Memory Interconnects with Variable Pitch
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Solution Overview
Problem
The development of 3D stacked memory devices requires a large number of fine pitch interconnects, which increases manufacturing costs and limits flexibility due to the need for through silicon vias (TSVs) or silicon interposers, especially when dealing with mixed substrate materials and the sharing of data lines across multiple memory chips, resulting in high costs per bit and limited bandwidth.
Innovation Solution
A memory device architecture that allows each memory die layer to drive a subset of data lines, using offset interconnects with varying pitch depending on the number of memory layers, enabling the use of conventional packaging techniques and reducing the number of mechanical connections, thereby lowering costs and increasing bandwidth as more memory layers are added.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of fine pitch interconnects are used to connect multiple memory die layers, then memory bandwidth is improved, but manufacturing cost increases and flexibility is limited
Solution Approach 1:
The patent segments the interconnect structure into multiple layers with different pitch values. Lower memory die layers use finer pitch interconnects to achieve higher bandwidth, while upper layers use coarser pitch interconnects to reduce manufacturing complexity and cost. This segmentation allows the system to achieve high overall bandwidth without requiring all interconnects to be fine pitch, thereby resolving the contradiction between bandwidth and manufacturing ease.
2Quantity of substance
If through silicon vias (TSVs) or silicon interposers are used to achieve fine pitch interconnects, then interconnect density is improved, but device complexity and manufacturing flexibility are reduced
Solution Approach 1:
The patent implements a dynamic interconnect pitch architecture where the pitch value changes depending on the memory die layer level. Upper layers utilize coarser pitch interconnects that can be manufactured using conventional techniques, while lower layers employ finer pitch interconnects. This dynamic variation in pitch eliminates the need for TSVs or silicon interposers throughout the entire structure, reducing device complexity and manufacturing flexibility requirements while maintaining necessary interconnect density where performance demands it.
3Manufacturing precision
If conventional packaging techniques are avoided to achieve fine pitch interconnects, then interconnect precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent applies local quality by assigning different pitch characteristics to different regions (memory die layers) of the stacked memory structure. Specifically, lower layers receive fine pitch interconnects for high precision requirements, while upper layers receive coarser pitch interconnects that can be manufactured using conventional packaging techniques. This localized differentiation allows the system to achieve high manufacturing precision only where necessary, thereby improving ease of manufacture overall without sacrificing critical interconnect precision.
Data Source
AI summary
A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.