Stress-Releasing Transistor for Select Transistor Oxide Breakdown
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in achieving low power and high speed operation due to excessive stress on the select transistor, leading to oxide breakdown, and struggle with increasing memory capacity while maintaining device size and integration.
Innovation Solution
Incorporating a stress-releasing transistor between the floating gate transistor and the select transistor, with a stress release ratio determined by the channel length and gate dielectric layer thickness, to alleviate stress on the select transistor during program operations and ensure effective read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a core device is adopted as the select transistor to achieve low power and high speed operation, then power consumption is reduced and operation speed is improved, but excessive stress on the select transistor causes oxide breakdown
Solution Approach 1:
A stress-releasing transistor is introduced as an intermediary component between the floating gate transistor and the select transistor. This intermediate device absorbs and redistributes the stress that would otherwise concentrate on the select transistor, preventing oxide breakdown while allowing the select transistor to operate at high speed and low power.
Solution Approach 2:
The stress management function is segmented from the select transistor by introducing a dedicated stress-releasing transistor. This separates the concerns of high-speed low-power operation (handled by the select transistor) from stress management (handled by the stress-releasing transistor), allowing each component to be optimized for its specific function.
2Productivity
If device size is decreased to achieve high integration degree, then memory capacity per area is improved, but stress management becomes more difficult
Solution Approach 1:
The stress-releasing transistor is merged with the existing memory cell structure by sharing the channel region and doping profiles with the select transistor. This integration allows stress management functionality to be added without proportionally increasing device area, maintaining high integration density while managing stress in deep sub-micron processes.
Data Source
AI summary
A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed.The stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor (1).