Oxide Semiconductor Transistor with Self-Aligned Top Gate
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Solution Overview
Problem
Silicon-based thin film transistors (TFTs) have low carrier mobility, complex manufacturing processes, and require high temperature processing, leading to parasitic capacitance and reduced operating speed due to overlapping gate and source/drain structures, which deteriorate transistor characteristics.
Innovation Solution
A transistor with an oxide semiconductor layer as the channel layer, including source and drain regions with a conductive impurity, a gate electrode, and a gate insulating layer extending onto the source and drain regions, minimizing parasitic capacitance and using low-temperature annealing to simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate and source/drain overlapping structure is used in silicon-based TFTs, then manufacturing is simplified, but parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The patent changes the material parameter from silicon-based semiconductor to oxide semiconductor, which fundamentally alters the electrical characteristics and allows for reduced parasitic capacitance effects while maintaining manufacturing simplicity through low-temperature processing
2Ease of manufacture
If silicon-based materials are used for the channel layer, then manufacturing processes are established, but carrier mobility is low and high temperature processing is required
Solution Approach 1:
The patent changes the semiconductor material parameter from silicon-based to oxide semiconductor, which provides higher carrier mobility and enables low-temperature processing while maintaining compatibility with existing TFT manufacturing approaches
Solution Approach 2:
The patent uses oxide semiconductor materials such as In-Ga-Zn-O composite oxides that combine multiple elements to achieve superior electrical characteristics including high carrier mobility and stability
3Speed
If gate and source/drain do not overlap, then parasitic capacitance is reduced, but parasitic resistive regions occur and transistor characteristics deteriorate
Solution Approach 1:
The patent changes the semiconductor material to oxide semiconductor, which has higher carrier mobility and different electrical characteristics that reduce the impact of parasitic resistance while allowing for non-overlapping gate and source/drain structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The oxide semiconductor layer enhances charge mobility, reduces parasitic capacitance, and simplifies the manufacturing process, resulting in higher operating speed and improved transistor characteristics without the need for crystallization or dehydrogenation processes.
Implementation Method 1
Parasitic capacitance may occur due to the overlapping portions between the gate and the source/drain and an operating speed may be reduced
Implementation Method 2
The source and drain regions may be regions into which a conductive impurity is injected
Implementation Method 3
low-temperature annealing to simplify manufacturing
Data Source
AI summary
Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.