TFT Array Substrate Composite Protective Layer

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Solution Overview

Problem

The stability of thin film transistor (TFT) array substrates is compromised due to de-oxygenation of metal oxide semiconductor layers caused by insulating layers, and the low etching rate of dry etching processes using Al2O3 or SiOx layers hinders large-scale production.

Innovation Solution

A TFT array substrate with a composite lamination structure in the semiconductor protective layer, comprising a metal oxide protective layer that prevents de-oxygenation and an organic insulating layer for easy etching, improving stability and etching speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If SiN x is used as the etching stop layer and gate insulating layer, then the etching performance is improved, but the metal oxide semiconductor layer undergoes de-oxygenation causing unstable TFT behavior

Engineering Contradiction:
Improveetching speedVSAvoidTFT stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the gate insulating layer into multiple layers: a SiN x layer (for etching stop function) and an Al 2 O 3 layer (for oxygen barrier function). This segmentation allows each layer to perform its specialized function without compromising the other, resolving the contradiction between etching performance and TFT stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The Al 2 O 3 layer acts as an intermediary between the SiN x layer and the metal oxide semiconductor layer. It prevents oxygen diffusion from the SiN x layer to the semiconductor layer, thereby protecting the semiconductor layer from de-oxygenation while allowing the SiN x layer to provide its etching stop function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If Al 2 O 3 or SiO x is used as the gate insulating layer, then the TFT stability is improved, but the etching rate decreases hindering large-scale production

Engineering Contradiction:
ImproveTFT stabilityVSAvoidetching speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The gate insulating structure is segmented into functional layers: SiN x layer dedicated to etching stop function (providing high etching rate) and Al 2 O 3 layer dedicated to oxygen barrier function (providing TFT stability). This segmentation resolves the contradiction by assigning different materials to different functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite gate insulating structure combining SiN x and Al 2 O 3 materials. This composite structure integrates the advantages of both materials: SiN x provides excellent etching stop properties while Al 2 O 3 provides superior oxygen barrier properties, achieving both high etching speed and TFT stability.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances the stability of TFT devices and facilitates large-scale production by preventing de-oxygenation of the semiconductor layer and increasing the etching speed of the insulating layers.

Implementation Method 1

a protective layer formed of metal oxide and being in contact with the semiconductor layer

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

an insulating layer formed of an organic insulating material, wherein the gate electrode is provided on the base substrate

Methodology Applied
Scientific EffectSelective etching:

Data Source

PatentEP2779249B1Thin film transistor array substrate
Publication Date: 2018.10.10 BOE TECHNOLOGY GROUP CO LTD
  • EP2779249B1 patent drawingFigure 1(a)~1(c)
  • EP2779249B1 patent drawingFigure 1(d)~1(f)
  • EP2779249B1 patent drawingFigure 2(a)~2(c)

AI summary

An embodiment of the present invention provides a TFT array substrate comprising: a base substrate (1) and thin film transistors. The thin film transistor comprises a gate electrode (2), a semiconductor layer (5), a semiconductor protective layer, a source electrode (8) and a drain electrode (9). The semiconductor protective layer is disposed adjacent to the semiconductor layer (5) and comprises a composite lamination structure, which comprises a protective layer formed of an insulating material capable of preventing de-oxygen of the semiconductor layer (5) and an insulating layer formed of an insulating material to be etched more easily.