SOI Non-Volatile Memory Structure with Floating Gate
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Solution Overview
Problem
Non-volatile memory (NVM) integration on standard CMOS technology requires additional masks or process steps, occupying a large area, and existing flash memory technologies face challenges in efficient data storage and retrieval.
Innovation Solution
A memory device structure implemented using silicon-on-insulator (SOI) technology with a crossbar configuration, incorporating non-insulative and insulative regions to form MOSFETs, where floating gates trap charge between semiconductor regions, allowing for compact and efficient data storage by adjusting threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory is integrated on standard CMOS technology using traditional flash memory structures, then data storage capability is achieved, but additional masks or process steps are required occupying a large area
Solution Approach 1:
The patent merges the non-volatile memory structure with standard CMOS technology by integrating floating gate regions directly into the MOSFET structure. The floating gates are formed between the source and drain regions using the same semiconductor processing steps, eliminating the need for separate NVM fabrication processes and reducing the overall area required.
Solution Approach 2:
The MOSFET structure serves dual functions: as a standard transistor for logic operations and as a non-volatile memory cell through the addition of floating gates. This multi-functionality allows the same structure to perform both computation and data storage, removing the need for dedicated NVM process steps and reducing area occupation.
2Reliability
If traditional flash memory structures are used, then data storage is achieved, but the structure occupies a large area requiring additional masks or process steps
Solution Approach 1:
The patent combines the flash memory structure with standard CMOS MOSFETs by forming floating gate regions within the same device structure. The floating gates are created using conventional semiconductor processing steps already present in CMOS fabrication, thereby merging NVM functionality into the existing process flow and reducing overall device complexity.
Solution Approach 2:
The floating gate regions are formed as part of the self-aligned CMOS fabrication process, where the same ion implantation and oxidation steps that create source and drain regions also define the floating gate structures. This self-service approach eliminates the need for separate masking and patterning steps specifically for NVM formation.
3Manufacturing precision
If floating gates are used to trap charge between semiconductor regions, then threshold voltage adjustment is improved, but the structure becomes more complex
Solution Approach 1:
The patent applies local quality by forming floating gate regions only in specific locations between source and drain regions where charge trapping is needed for memory functionality. The doping profiles and oxide layer thicknesses are locally optimized to achieve precise threshold voltage control in the floating gate regions while maintaining standard MOSFET characteristics in other areas.
Solution Approach 2:
The patent achieves threshold voltage adjustment by changing the charge state of the floating gates through controlled charge trapping and release. By varying the amount of charge stored in the floating gates, the threshold voltage of the MOSFET can be precisely controlled, enabling multi-state memory operation without increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SOI-based memory device achieves efficient data storage and retrieval with improved threshold voltage adjustment, enabling compact integration and enhanced performance compared to traditional NVM technologies.
Implementation Method 1
applying the voltage traps charge between the first insulative region and the second region
Data Source
AI summary
Certain aspects of the present disclosure provide a memory device. One example memory device generally includes a first semiconductor region having a first region, a second region, and a third region, the second region being between the first region and the third region and having a different doping type than the first region and the third region. In certain aspects, the memory device also includes a first non-insulative region, a first insulative region being disposed between the first non-insulative region and the first semiconductor region. In certain aspects, the memory device may include a second non-insulative region, and a second insulative region disposed between the second region and the second non-insulative region, wherein the first insulative region and the second insulative region are disposed adjacent to opposite sides of the second region.