Symmetric Vertical Nanowire SRAM Cell Layout
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Solution Overview
Problem
The existing layouts of SRAM cells using vertical nanowire FETs suffer from asymmetric transistor arrangements, leading to deteriorated device characteristics, reduced reliability, and lower yield due to increased off-current and power consumption from excessive scaling.
Innovation Solution
A highly symmetric layout structure for SRAM cells using vertical nanowire FETs is implemented, where transistors are arranged to ensure mutual connections and side-by-side configurations in specific directions, and bit line pairs are connected through a peripheral part to reduce resistance and suppress crosstalk noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are excessively scaled to improve integration degree and operating speed, then device density and speed are improved, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional vertical nanowire FETs. This dimensional change allows the transistor channel to extend vertically rather than horizontally, enabling continued scaling and integration density improvement while maintaining better control over off-current and power consumption through the vertical architecture's inherent electrical characteristics
2Area of stationary object
If asymmetric transistor arrangement is used in SRAM cell layout, then area is reduced, but device characteristics deteriorate and reliability reduces
Solution Approach 1:
The patent deliberately introduces asymmetric dummy transistors around the peripheral region of the SRAM cell. These dummy structures compensate for the inherent asymmetry in the access transistor connections to bit lines, creating a more balanced electrical environment that improves device characteristics and reliability while maintaining compact area
3Area of stationary object
If asymmetric transistor arrangement is used in SRAM cell layout, then area is reduced, but yield reduces
Solution Approach 1:
The asymmetric dummy transistor structures are strategically placed to compensate for process variations and manufacturing tolerances. This asymmetric compensation approach improves the uniformity of device characteristics across the wafer, thereby enhancing yield despite the asymmetric layout configuration
Data Source
AI summary
A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.