Polysilicon Gate Protection During Replacement Gate Process
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Solution Overview
Problem
As semiconductor feature sizes decrease, traditional flash memory cells with polysilicon gates and silicon dioxide dielectrics reach performance limits, leading to increased leakage current and power consumption, necessitating the integration of high κ metal gate (HKMG) technology to enhance performance.
Innovation Solution
The method involves forming a silicon nitride hard mask over polysilicon control gates in embedded flash memory devices, performing a selective etch to remove oxide hard masks, and using chemical mechanical polishing (CMP) to thin interlayer dielectric layers while protecting the polysilicon gates, thereby preventing complete silicide formation and maintaining sufficient polysilicon thickness to reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate thickness is reduced to enable HKMG integration, then device performance and leakage reduction are improved, but polysilicon loss and charge leakage increase
Solution Approach 1:
A silicon nitride hard mask is deposited over the polysilicon control gate before the RPG process. This preliminary protective layer prevents polysilicon loss during subsequent etching and CMP operations, allowing the gate thickness to be reduced for HKMG integration while maintaining sufficient polysilicon volume to prevent charge leakage.
Solution Approach 2:
The patent applies different treatments to different regions: the silicon nitride hard mask is selectively retained over the flash memory control gates while being removed from other areas. This localized protection ensures that only the necessary polysilicon gates are preserved, enabling HKMG integration in non-memory regions while maintaining polysilicon integrity in memory regions.
2Power
If traditional polysilicon gates are replaced with metal gates, then dielectric constant and switching speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the integrated circuit into different regions: flash memory device regions that retain traditional polysilicon gates and HKMG transistor regions that use metal gates. This segmentation allows each region to be optimized independently, enabling HKMG technology integration without requiring complete process overhaul across the entire chip.
Solution Approach 2:
The silicon nitride hard mask serves as an intermediary protective layer during the RPG process. It mediates between the conflicting requirements of reducing polysilicon thickness for HKMG integration and maintaining sufficient thickness to prevent charge leakage, enabling a transition path from traditional to advanced gate structures.
3Productivity
If feature sizes are decreased to increase device density, then number of devices per unit area is improved, but leakage current and power consumption increase
Solution Approach 1:
The patent changes the gate structure parameters by integrating HKMG technology with higher dielectric constant materials and optimized metal gate thickness. This parameter change allows smaller feature sizes to achieve acceptable leakage levels, enabling continued device scaling without proportional increases in power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a sufficient polysilicon thickness for the control gates, reducing charge leakage and power consumption, and enabling the integration of HKMG transistors with a metal gate electrode positioned lower than the silicide layer, enhancing the performance and functionality of embedded flash memory devices.
Implementation Method 1
using chemical mechanical polishing (CMP) to thin interlayer dielectric layers while protecting the polysilicon gates
Implementation Method 2
performing a selective etch to remove oxide hard masks
Data Source
AI summary
The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.