Semiconductor Word Line Formation via Anisotropic Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
A semiconductor device structure is formed using a process that includes shallow trench isolation, gate dielectric material deposition, and a conductive layer filling with an anisotropic etching back process, eliminating the need for photolithography in forming word lines, which improves electrical properties and reduces manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to form word lines, then manufacturing process can be completed, but word line width uniformity deteriorates and misalignment occurs
Solution Approach 1:
The patent extracts and removes the photolithography step from the word line formation process, replacing it with a self-aligned deposition and etching back process. This eliminates the source of width variation and misalignment inherent in photolithography, directly improving manufacturing precision while reducing process complexity.
Solution Approach 2:
The word lines are formed through a self-aligned process where the conductive layer is deposited conformally over the gate stacks and then etched back. The gate stacks themselves serve as the alignment reference, eliminating the need for separate photolithography alignment steps and ensuring uniform word line widths.
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency improves and costs lower, but fabrication process reliability deteriorates
Solution Approach 1:
The self-aligned formation process ensures that word lines are automatically positioned correctly relative to gate stacks without requiring additional alignment steps. This maintains high precision even as feature sizes decrease, preserving fabrication reliability while enabling increased functional density.
Solution Approach 2:
The patent changes the formation mechanism from optical-based photolithography to physical deposition and etching processes. This parameter change allows for better control at smaller dimensions, maintaining reliability while supporting continued scaling for higher productivity.
3Reliability
If conventional processes are used to form word lines, then manufacturing can proceed, but contact resistance increases and electrical properties deteriorate
Solution Approach 1:
By removing the photolithography step and using direct deposition followed by etching back, the patent achieves better contact between word lines and underlying structures. This eliminates the need for additional alignment tolerances and reduces contact resistance, improving electrical properties without increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical properties of memory cells and transistors by maintaining uniform word line widths, reduces manufacturing costs, and simplifies the process, while preventing misalignment and lowering contact resistance.
Implementation Method 1
performing an anisotropic etching back process to remove a portion of the conductive layer
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.