Common Drain Semiconductor Device Interleaved Active Regions
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Solution Overview
Problem
Semiconductor devices with a common drain configuration face challenges in achieving uniform current density and low source-to-source on-resistance due to substrate and back metal resistance, which can increase costs and risk wafer cracking when attempting to reduce thickness.
Innovation Solution
The semiconductor device structure incorporates a substrate with interleaved active regions and conductive layers, eliminating the need for a third conductive layer, and optimizing gate trench structures to enhance current flow, thereby reducing source-to-source on-resistance without requiring a thinner wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wafer thickness is reduced to decrease substrate resistance, then the source-to-source on-resistance is reduced, but the risk of wafer cracking increases
Solution Approach 1:
An intermediate conductive layer is introduced between the substrate and the back metal contact. This intermediate layer serves as a mediator that provides additional current conduction paths, effectively reducing the substrate resistance contribution to source-to-source on-resistance without requiring the substrate to be thinner, thereby maintaining wafer mechanical strength.
Solution Approach 2:
The patent changes the electrical parameters of the substrate region by introducing additional conductive layers and modifying the substrate doping profile in the region between the two transistors. These parameter changes reduce the effective resistance without altering the physical thickness of the substrate, thus avoiding mechanical strength degradation.
2Reliability
If a back metal layer is added to reduce substrate resistance, then the source-to-source on-resistance is reduced, but the device cost increases
Solution Approach 1:
The conductive layers in the patent serve multiple functions: they act as contact regions for reducing resistance, serve as current conduction paths, and can be integrated with existing interconnect structures. This multi-functionality allows the structure to reduce source-to-source on-resistance without requiring an additional dedicated back metal layer, thereby controlling device cost.
Solution Approach 2:
The patent merges the function of the back metal contact with the substrate contact regions by forming conductive layers that extend from the surface into the substrate. This consolidation eliminates the need for a separate back metal layer while achieving the same resistance reduction effect, thus reducing manufacturing complexity and cost.
3Reliability
If the distance between source areas is reduced to decrease on-resistance, then the source-to-source on-resistance is reduced, but the device area is reduced limiting current density uniformity
Solution Approach 1:
Instead of reducing the lateral distance between source areas, the patent introduces vertical current conduction paths through additional conductive layers that extend into the substrate. This dimensional transition from lateral to vertical conduction allows the device to maintain a larger area for current density uniformity while still achieving reduced on-resistance through the vertical conduction paths.
Data Source
AI summary
In one embodiment, a common drain semiconductor device includes a substrate, having two transistors integrated therein. The substrate also includes a plurality of active regions on a major surface of the substrate. The active regions of each transistor may be interleaved.